Efficient Modulo $2^{n}+1$ Multipliers

Chen, Jian Wen; Yao, Ruo He; Wu, Wei

doi:10.1109/tvlsi.2010.2080330

Cited by 21 publications

(10 citation statements)

References 20 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The results of the proposed architecture with CSA (Proposed-I) and prefix-based adders (Proposed-II) are presented in Table 7 and Table 8, respectively. 16,17,18,19,20,21]. Proposed architecture I save area in the range of 23% -44%, whereas the proposed architecture II reduces the area in the range of 10% -32% compared to existing MBE architectures.…”

Section: Fpga Synthesismentioning

confidence: 92%

“…A hybrid input representation approach with a radix-4 booth encoding scheme utilizing one binary-weighted operand and diminished-1 input representation for the other operand is explained in [17]. The architecture supports both odd and even value of n. The authors have achieved a compact area with an enhanced speed compared to the existing multipliers.…”

Section: Review Of Existing Workmentioning

confidence: 99%

“…Modified Booth Encoded (MBE) modulo multiplication scheme is relatively faster and can handle both signed, and unsigned numbers, the researcher's attention turned towards it, and many modifications of the same are reported in recent years [15,16,17,18,19,20]. The residue multipliers based on diminished-1 input representation in array and bit pair recoding booth algorithm are seen in [16,17,21]. Based on the conducted survey, it is evident that there is no work based on a signed array modulo multiplication scheme reported in the literature.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Hardware Implementation of Residue Multipliers based Signed RNS Processor for Cryptosystems

Elango¹,

Sampath²

2020

Informacije MIDEM

View full text Add to dashboard Cite

The Residue Number System (RNS) characterize large integer numbers into smaller residues using moduli sets to enhance the performance of digital cryptosystems. A parallel Signed Residue Multiplication (SRM) algorithm, VLSI parallel array architecture for balanced (2 n-1, 2 n , 2 n +1) and unbalanced (2 k-1, 2 k , 2 k +1) word-length moduli are proposed which in turn are capable of handling signed input numbers. Balanced 2 n-1 SRM is used as a reference to design an unbalanced 2 k-1 and 2 k +1. The synthesized results show that the proposed 2 n-1 SRM architecture achieves 17% of the area, 26% of speed, and 24% of Power Delay Product (PDP) improvement compared to the Modified Booth Encoded (MBE) architectures discussed in the review of the literature. The proposed 2 n +1 SRM architecture achieves 23% of the area, 20% of speed, and 22% of PDP improvement compared to recent counterparts. There is a significant improvement in the results due to the fully parallel coarsely grained approach adopted for the design, which is hardly attempted for signed numbers using array architectures. Finally, the proposed SRM modules are used to design {2 n-1, 2 n , 2 n +1} special moduli set based RNS processor, and the real-time verification is performed on Zynq (XC7Z020CLG484-1) Field Programmable Gate Array (FPGA).

show abstract

Section: Fpga Synthesismentioning

confidence: 92%

Section: Review Of Existing Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Hardware Implementation of Residue Multipliers based Signed RNS Processor for Cryptosystems

Elango¹,

Sampath²

2020

Informacije MIDEM

View full text Add to dashboard Cite

show abstract

“…Improved RNS addition [2][3][4], multiplication [5][6][7][8], and conversion [9][10][11][12] algorithms, sometimes based on new encodings [13], appear regularly in the literature. Moduli of the form 2 δ are popular due to ease of designing fast adders, especially for δ 1 [14] and δ 3 [16], where addition circuits with only one n-bit adder in the critical path are possible.…”

Section: A Residue Number System (Rns)mentioning

confidence: 99%

On building general modular adders from standard binary arithmetic components

Jaberipur

Parhami

Nejati

2011

2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR)

View full text Add to dashboard Cite

show abstract

“…The hardware area and delay of the proposed and reference designs are first estimated by the unit-gate model [Che11]. The unit-gate areas and delays of the proposed (This) and reference (Ref) designs are compared in Table 4.1, where % = (RefThis)/Ref×100%.…”

Section: Unit-gate Analysismentioning

confidence: 99%

New algorithms and VLSI architectures for efficient RNS computations

Tay¹

View full text Add to dashboard Cite

Residue Number System (RNS) is a non-weighted number system emerging as a promising substitute of two's complement number system for data representation in high-speed and lowpower digital signal processing. In RNS, arithmetic operations, such as addition, subtraction and multiplication, can be carried out at a faster speed due to the avoidance of carry propagation. Nonetheless, the arithmetic operations such as sign detection, scaling, base transformation and error decoding, are generally more difficult to be implemented in RNS. This thesis aims to tackle these difficult RNS operations by designing simple and efficient algorithms and architectures. In this thesis, a fast and area efficient 2 n signed integer RNS scaler for the moduli set {2 n −1, 2 n , 2 n +1} is proposed. The complex sign detection circuit has been obviated and replaced by simple logic manipulation of some bit-level information of intermediate magnitude scaling results. As a result, the proposed architecture achieves at least 21.6% of area saving, 28.8% of speedup and 32.5% of total power reduction compared to the state-of-art designs. In addition, a new concept of base transformation is introduced to reduce the overall arithmetic processing costs of multi-base RNS. The exploration into this new concept is motivated by the overkill of arithmetic operator sizes in RNS-based digital signal processors (DSPs) due to the List of Abbreviations CRT Chinese Remainder Theorem CSA Carry Save Adder

show abstract

Efficient Modulo $2^{n}+1$ Multipliers

Cited by 21 publications

References 20 publications

Hardware Implementation of Residue Multipliers based Signed RNS Processor for Cryptosystems

Hardware Implementation of Residue Multipliers based Signed RNS Processor for Cryptosystems

On building general modular adders from standard binary arithmetic components

New algorithms and VLSI architectures for efficient RNS computations

Contact Info

Product

Resources

About