Efficient modulo 2
            <sup>
              <i>n</i>
            </sup>
            +1 multipliers for diminished-1 representation

Chen, Jian Wen; Yao, Ruo He

doi:10.1049/iet-cds.2009.0284

Cited by 26 publications

(11 citation statements)

References 13 publications

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“…Efficient modulo 2 n + 1 addition and multiplication units for diminished-1 operands [10]- [14] have been proposed. Many DSP applications, e.g., symmetric FIR filters, perform a large number of Add-Multiply (AM) operations.…”

Section: Introductionmentioning

confidence: 99%

Fused modulo 2n + 1 Add-Multiply unit for diminished-1 operands

Tsoumanis

Pekmestzi

Efstathiou

2016

2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST)

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Complex arithmetic operations dominate Digital Signal Processing (DSP) applications heavily degrading their performance. Targeting to accelerate the Residue Number Systemsbased DSP applications, we optimize the design of the Add-Multiply (AM) operation with modulo 2 n + 1 diminished-1 operands by incorporating the direct recoding of the sum of two numbers in its Modified Booth form. Compared to the conventional allocation of an adder and a subsequent multiplier, the proposed fused AM design yields delay, area and power gains.

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Section: Introductionmentioning

confidence: 99%

Fused modulo 2n + 1 Add-Multiply unit for diminished-1 operands

Tsoumanis

Pekmestzi

Efstathiou

2016

2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST)

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“…properties. The full-combinatorial based implementation of modulo multiplier using the properties of special modulo arithmetic have received wide spread attention [Hias92], [Wrzy93], [Wang96a], [Wang96b], [Ma98], [Zimm99], [Efst04a], [Efst05], [Sous05], [Verg07], [Chen10].…”

Section: Motivationmentioning

confidence: 99%

“…However, the diminished-1 number system proposed in [Leib76] is most prevalent in modulo 2 n +1 multiplier designs [Wang96b], [Efst05], [Ma98], [Sous05], [Chen10]. The diminished-1 multiplier can be further classified on the basis of the encoding employed for the multiplier bits: (a) Non-encoded multipliers, e.g., [Wang96b] and [Efst05] (b) Radix-4 Booth encoded multipliers, e.g., [Ma98], [Sous05] and [Chen10].…”

Section: Non-encoded Modulo 2 N −1 Multipliermentioning

confidence: 99%

“…In [Chen10], a more regular partial product generation scheme and a simpler expression for correction term were derived for radix-4 Booth encoded modulo 2 n +1 multiplication using diminished-1 representation. The product was given by ∑ and C' is the diminished-1 representation of the constant one, i.e., an allzeros vector.…”

Section: )mentioning

confidence: 99%

“…Types B and C radix-4 Booth encoded RNS multipliers use the same modulo 2 n −1 multiplier [Efst04a], but the former uses the design [Chen10] and the latter uses the design [Sous05] for the modulo 2 n +1 multiplier. Types D and E non-encoded RNS multipliers use the modulo 2 n −1 multiplier of [Zimm99].…”

Section: Performance Analysismentioning

confidence: 99%

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Novel modulo multipliers for moduli 2^n-1, 2^n and 2^n+1.

Muralidharan¹

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Long word-length integer multiplication is widely acknowledged as the bottleneck operation in public key cryptographic and signal processing algorithms. Residue Number System (RNS) has emerged as a promising alternative number representation for the design of faster and low power multipliers owing to its merit to distribute a long integer multiplication into several shorter and parallel modulo multiplications. To maximize the advantages offered by the RNS multiplier, judicious choice of moduli that constitute the RNS base and design of efficient modulo multipliers are imperative. In this thesis, special modulo 2 n −1, modulo 2 n and modulo 2 n +1 multipliers are studied. By manipulating the number theoretic properties of special moduli, 2 n −1, 2 n and 2 n +1, new low-power and low-area modulo multipliers are proposed. The modulo 2 n −1 multiplier is typically the non-critical datapath among all modulo multipliers in the RNS multiplier. This timing slack can be exploited to lower the area as well as power dissipation without compromising the performance of the RNS multiplier. A family of radix-8 Booth encoded modulo 2 n −1 multipliers with delay adaptable to match the RNS delay is proposed. The modulo 2 n −1 multiplier delay is made scalable by controlling the word-length k of the Ripple Carry Adder (RCA) that computes the necessary hard multiple, i.e., three time the multiplicand, of the radix-8 Booth encoding algorithm. The hard multiple and the simple multiples are consistently represented in partially-redundant biased forms. The compensation constant that negates the effect of the biased representation is proven to be a single constant n-bit word for all valid combinations of n and k. The adaptive delay of the modulo 2 n −1 multiplier is corroborated by synthesis results based on CMOS implementations. In an imbalanced word-length moduli set based RNS multiplier, where the critical modulo m multiplier delay is significantly greater than the non-critical modulo 2 n −1 multiplier delay, k = n and k = n/3 when n is not divisible by three and divisible by three, respectively, are recommended for maximal area-power savings. New radix-8 Booth encoded modulo 2 n −1 and modulo 2 n +1 multipliers that are equally applicable in critical and non-critical modulo channels as well as balanced and imbalanced viii word-length moduli sets are also proposed. Custom adders called Hard Multiple Generators (HMGs) that exclusively compute the required hard multiples of radix-8 Booth encoded modulo 2 n −1 and modulo 2 n +1 multiplications are designed. The parallel-prefix implementations of the proposed modulo 2 n −1 and modulo 2 n +1 HMGs employ the fewest number of prefix levels and hence are the fastest adders for this application. The moduloreduced partial products were generated with no accompanying bias in the proposed modulo 2 n −1 multiplier while the inevitable bias was succinctly expressed as three n-bit words in the proposed modulo 2 n +1 multiplier. The savings in area and power dissipation of the proposed radix-8 Booth ...

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