Efficient multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11ad applications

Ajaz, Sabooh; Lee, Hanho

doi:10.1016/j.vlsi.2015.05.001

Cited by 6 publications

(4 citation statements)

References 17 publications

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“…In recent years, research on LDPC codes has centered around structured LDPC codes known as the quasi-cyclic low-density parity-check (QC-LDPC) codes [9][10][11][12][13], which have demonstrated great advantages over other types of LDPC codes in terms of hardware implementation and excellent error performance over noisy channels. In QC-LDPC codes, the parity-check matrix consists of either cyclic permutation submatrixes or zero matrixes of the same size, determining the interconnection between the check node processing units (CNUs) and variable node processing units (VNUs).…”

Section: Introductionmentioning

confidence: 99%

Low-Complexity Multi-Size Circular-Shift Network for 5G New Radio LDPC Decoders

Tan

Nguyen

Lee

2022

Sensors

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This paper presents a low-complexity multi-size circular-shift network (MCSN) structure for 5th-generation (5G) New Radio (NR) quasi-cyclic low-density parity-check (QC-LDPC) decoders. In particular, a fine-coarse approach-based multi-size cyclic shift network, which decomposes the cyclic shift size into fine part and coarse part, is introduced. The proposed MCSN structure is composed of a pre-rotator performing the fine part of the cyclic shift, and a main rotator executing the coarse part of the cyclic shift. In addition, a forward routing circular-shift (FRCS) network, which is based on the barrel shifter and the forward routing process is presented. The proposed switch network is able to support all 51 different submatrix sizes as defined in the 5G NR standard through an efficient forward routing switch network and help reduce the hardware complexity using a cyclic shift size decomposition method. The proposed MCSN is analyzed, and indicates a substantial reduction in the hardware complexity. The experimental results on TSMC 65-nm CMOS technology show that the proposed MCSN structure for 5G NR LDPC decoder offers an area saving up to 56.75% compared to related works in the literature.

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Section: Introductionmentioning

confidence: 99%

Low-Complexity Multi-Size Circular-Shift Network for 5G New Radio LDPC Decoders

Tan

Nguyen

Lee

2022

Sensors

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“…Over recent years, research on LDPC codes has been focused on structured LDPC codes known as quasi-cyclic low-density parity-check (QC-LDPC) codes [8][9][10][11][12], which exhibit advantages over other types of LDPC codes with respect to the hardware implementations of encoding and decoding using simple shift registers and logic circuits. A low-complexity encoder can be realized by using QC-LDPC codes, due to the sparseness of the parity check matrix.…”

Section: Introductionmentioning

confidence: 99%

Efficient QC-LDPC Encoder for 5G New Radio

2019

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This paper presents a novel efficient encoding method and a high-throughput low-complexity encoder architecture for quasi-cyclic low-density parity-check (QC-LDPC) codes for the 5th-generation (5G) New Radio (NR) standard. By storing the quantized value of the permutation information for each submatrix instead of the whole parity check matrix, the required memory storage size is considerably reduced. In addition, sharing techniques are employed to reduce the hardware complexity. The encoding complexity of the proposed method was analyzed, and indicated a substantial reduction in the required area as well as memory storage when compared with existing state-of-the-art encoding approaches. The proposed method requires only 61% gate area, and 11% ROM storage when compared with a similar LDPC encoder using the Richardson–Urbanke method. Synthesis results on TSMC 65-nm complementary metal-oxide semiconductor (CMOS) technology with different submatrix sizes were carried out, which confirmed that the design methodology is flexible and can be adapted for multiple submatrix sizes. For all the considered submatrix sizes, the throughput ranged from 22.1–202.4 Gbps, which sufficiently meets the throughput requirement for the 5G NR standard.

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“…To meet these demands, multi-gigabit data transmission rate standards have been proposed, such as IEEE 802.11ad [2] for gigabit wireless local area networks (WLANs) and IEEE 802.15.3c for wireless personal area networks (WPANs). Fully parallel LDPC decoders, which directly map row and column processors together according the Tanner graph interconnection network of the corresponding parity check matrix, can generally provide very high throughput [13,14] while operating at low clock rates. However, as the parallelism increases, a large number of processing units and wires inhibits efficient design, and results in larger hardware and interconnect complexity.…”

Section: Introductionmentioning

confidence: 99%

“…For LDPC decoders, one of the major design challenges is to achieve a better area and throughput tradeoff. An attractive design approach for area reduction is a half-row, parallel layered decoder [11], compared to a fully parallel layered decoder [13,14]. In this approach, the parity check matrix is split into two nearly-separate halves in the vertical direction.…”

Section: Introductionmentioning

confidence: 99%

An Area-efficient Half-row Pipelined Layered LDPC Decoder Architecture

Ajaz¹,

Nguyen²,

Lee³

2017

JSTS

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This paper presents an area-efficient halfrow pipelined layered low-density parity check (LDPC) decoder architecture for IEEE 802.11ad applications. The proposed decoder achieves a good tradeoff between throughput and area because of its ability to overcome the low-throughput bottleneck in conventional half-row decoders and the highcomplexity bottleneck in fully parallel decoders. Synthesis results using TSMC 40 nm CMOS technology shows much better throughput at 10.84 Gbps and superior area efficiency, compared to previously reported LDPC decoders.

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Efficient multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11ad applications

Cited by 6 publications

References 17 publications

Low-Complexity Multi-Size Circular-Shift Network for 5G New Radio LDPC Decoders

Low-Complexity Multi-Size Circular-Shift Network for 5G New Radio LDPC Decoders

Efficient QC-LDPC Encoder for 5G New Radio

An Area-efficient Half-row Pipelined Layered LDPC Decoder Architecture

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