Efficient multiply-add unit specified for DSPs utilizing low-power pipeline modulo 2n+1 multiplier

Akbarzadeh, Negar; Timarchi, Somayeh; Hamidi, Amir Abbas

doi:10.1109/iranianmvip.2015.7397518

Cited by 4 publications

(5 citation statements)

References 15 publications

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“…2 reveals that the architectures in [12,33,34] consume considerably higher static and average power (in mW) than the proposed SFMAC architecture. The architectures in [35,36] are examined for 16-bit operations at 1 V and 8-bit operations at 1.8 V in 90 and 180 nm technologies. Even though the existing work described in [35,36] requires less power than the proposed SFMAC (the existing circuit's performance analysis is done with a supply voltage less than 2 V, while the SFMAC uses a supply voltage of 2 V), these two existing implementations can only execute MAC operations on unsigned fixed-point numbers.…”

Section: Esc Blockmentioning

confidence: 99%

“…Even though the existing work described in [35,36] requires less power than the proposed SFMAC (the existing circuit's performance analysis is done with a supply voltage less than 2 V, while the SFMAC uses a supply voltage of 2 V), these two existing implementations can only execute MAC operations on unsigned fixed-point numbers. As a result, the MAC architectures in [35,36] have a restricted scope. Although the architecture defined in [37] is implemented in 180 nm technology with a 1.8 V supply voltage for 16-MAC operation, it consumes substantially more power than the SFMAC architecture.…”

Section: Esc Blockmentioning

confidence: 99%

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An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation

Sarma¹,

Bhargava²,

Kotecha³

2022

Computers, Materials &Amp; Continua

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In the era of digital signal processing, like graphics and computation systems, multiplication-accumulation is one of the prime operations. A MAC unit is a vital component of a digital system, like different Fast Fourier Transform (FFT) algorithms, convolution, image processing algorithms, etcetera. In the domain of digital signal processing, the use of normalization architecture is very vast. The main objective of using normalization is to perform comparison and shift operations. In this research paper, an evolutionary approach for designing an optimized normalization algorithm is proposed using basic logical blocks such as Multiplexer, Adder etc. The proposed normalization algorithm is further used in designing an 8 × 8 bit Signed Floating-Point Multiply-Accumulate (SFMAC) architecture. Since the SFMAC can accept an 8-bit significand and a 3-bit exponent, the input to the said architecture can be somewhere between −(7.96872) 10 to + (7.96872) 10 . The proposed architecture is designed and implemented using the Cadence Virtuoso using 90 and 130 nm technologies (in Generic Process Design Kit (GPDK) and Taiwan Semiconductor Manufacturing Company (TSMC), respectively). To reduce the power consumption of the proposed normalization architecture, techniques such as "block enabling" and "clock gating" are used rigorously. According to the analysis done on Cadence, the proposed architecture uses the least amount of power compared to its current predecessors.

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Section: Esc Blockmentioning

confidence: 99%

Section: Esc Blockmentioning

confidence: 99%

An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation

Sarma¹,

Bhargava²,

Kotecha³

2022

Computers, Materials &Amp; Continua

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“…The delay of the unsigned fixed-point architecture in [27] is lesser than the proposed architecture because the operating frequency of the said architecture is much larger than the proposed SFMAC architecture. The performance of [28,29] are evaluated in 90 nm and 180 nm technologies for 16-bit operations at 1 V and 8-bit operations at 1.8 V respectively. Though, the power consumptions of the existing work mentioned in [28,29] are lesser than proposed SFMAC architecture (the existing circuit՚s performance analysis is performed in supply voltage lesser than 2 V whereas for the SFMAC the supply voltage is 2 V).…”

Section: 1mentioning

confidence: 99%

“…The performance of [28,29] are evaluated in 90 nm and 180 nm technologies for 16-bit operations at 1 V and 8-bit operations at 1.8 V respectively. Though, the power consumptions of the existing work mentioned in [28,29] are lesser than proposed SFMAC architecture (the existing circuit՚s performance analysis is performed in supply voltage lesser than 2 V whereas for the SFMAC the supply voltage is 2 V). Still, these two existing architectures are capable of performing the MAC operation on a fixed point unsigned number only.…”

Section: 1mentioning

confidence: 99%

“…Still, these two existing architectures are capable of performing the MAC operation on a fixed point unsigned number only. Therefore, the existing MAC architectures mentioned in [28,29] have limited scope. Though the architectures mentioned in [30] are implemented in 180 nm technology and 1.8 V supply voltage for 16-bit MAC operation, the power consumption is way more than the SFMAC architecture.…”

Section: 1mentioning

confidence: 99%

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Bulletin of the Polish Academy of Sciences: Technical Sciences

Sarma¹,

Bhargava²,

Jain³

2020

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Digital system algorithms such as FFT algorithms, convolution, image processing algorithm, etc. deploy Multiply and Accumulate (MAC) unit as an evaluative component. The efficiency of a MAC typically relies on the speed of operation, power dissipation, and chip area along with the complexity level of the circuit. In this research paper, a power-delay-efficient signed-floating-point MAC (SFMAC) is proposed using Universal Compressor based Multiplier (UCM). Instead of having a complex design architecture, a simple multiplexer-based circuit is used to achieve a signed-floating output. The 8£8 SFMAC can take 8-bit mantissa and 3-bit exponent and therefore, the input to the SFMAC can be in the range of -(7.96875) 10 to +(7.96875) 10 . The design and implementation of the proposed architecture is executed on the Cadence Spectre tool in GPDK 90 nm and TSMC 130 nm CMOS, which proves as power and delay efficient.

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Application of ameliorated Harris Hawks optimizer for designing of low-power signed floating-point MAC architecture

Sarma

Bhargava

Jain

et al. 2021

Neural Comput & Applic

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Efficient multiply-add unit specified for DSPs utilizing low-power pipeline modulo 2n+1 multiplier

Cited by 4 publications

References 15 publications

An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation

An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation

Bulletin of the Polish Academy of Sciences: Technical Sciences

Application of ameliorated Harris Hawks optimizer for designing of low-power signed floating-point MAC architecture

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