Efficient nanoscale VLSI standard cell library characterization using a novel delay model

Miryala, Sandeep; Kaur, Baljit; Bulusu, Anand; Manhas, S. K.

doi:10.1109/isqed.2011.5770767

Cited by 15 publications

(6 citation statements)

References 2 publications

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“…In case the nMOS operates in linear region when V I = V C , a similar equation (same as 18) comes into picture. This can be easily inferred by using (5) of earlier work on inverters reported in [8]. Further, we make the following observations from (17):…”

Section: B Case Ii: V I (T R ) > V C (For Fast Input Transitions)mentioning

confidence: 73%

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Efficient static D-latch standard cell characterization using a novel setup time model

Sharma

Sharma²,

Dasgupta

et al. 2015

Sixteenth International Symposium on Quality Electronic Design

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In this paper we propose a simple setup time model for a transmission gate based static latch, which we later use to simplify standard cell library characterization methodology. We propose a simple model for the setup time which relates it linearly with input transition time (T R ) and load capacitance (C L ). We also derive the region of validity of our model in the T R , C L space. We derive the relationship of the model coefficients and the model's region of validity with the size of CMOS latch standard cell. We then derive simple expressions relating our model coefficients with the supply voltage, threshold voltage, and temperature variations. We use these relationships to simplify latch setup time characterization methodology, eliminating the necessity of about 67% HSPICE simulations. We show that our model and method of improving the characterization process are valid with the technology scaling and realistic input signals. We observe that the value of setup time obtained using our model based approach for latch characterization differ from their corresponding HSPICE based method by a maximum (average) of 3.2% (1.5%).

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Section: B Case Ii: V I (T R ) > V C (For Fast Input Transitions)mentioning

confidence: 73%

“…Which have issues due to extensive computational time and requires numerous SPICE simulations. Authors in [8,9] have derived delay models to reduce the standard cell library characterization time. Which are only for basic combinational cells.…”

Section: Introductionmentioning

confidence: 99%

Efficient static D-latch standard cell characterization using a novel setup time model

Sharma

Sharma²,

Dasgupta

et al. 2015

Sixteenth International Symposium on Quality Electronic Design

Self Cite

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“…A number of characterization methodologies were proposed by many researchers in the aim of increasing the precision of the models ignoring the large simulation time [10][11][12][13]. In his paper J. Jianhua et al state that the choice of input parametes (index1, index2) in the timing LUT impacts the accuracy [10].…”

Section: Introductionmentioning

confidence: 99%

“…However, the model is based on an inverter. This method allows to save more than half (51%) of SPICE simulations time when characterizing a logic cell without affecting the accuracy [13]. In this work the simulation's time is still consequent.…”

Section: Introductionmentioning

confidence: 99%

New voltage and temperature scalable gate delay model applied to a 14nm technology

Charafeddine

Ouardi

2020

IJEECS

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<p>The following work shows an innovative approach to model the timing of standard cells. By using mathematical models instead of the classical SPICE-based characterization, a high amount of CPU (Central Processing Unit) cores is saved and less amount of data is stored. In the present work, characterization of cells of a standard cell library is done in an hour whereas it is done in 650 hours with the classical method. Also, a method for validating and verification of the precision of the modelled data is presented by comparing them on a implemented circuit. The output of implementations shows less than 3% of error between the two methods.</p>

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“…An accurate analytical propagation delay model of nano-CMOS circuits has been derived in [6] based on modified α-power law current model. A look-up table approach for efficient delay characterization of nano scale VLSI logic circuits is presented in [7]. An approach for optimization of digital integrated circuits using geometric programming technique is described in [8].…”

Section: Introductionmentioning

confidence: 99%

Modeling and Design of a Nano Scale CMOS Inverter for Symmetric Switching Characteristics

Mukhopadhyay

Pandit

2012

VLSI Design

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This paper presents a technique for the modeling and design of a nano scale CMOS inverter circuit using artificial neural network and particle swarm optimization algorithm such that the switching characteristics of the circuit is symmetric, that is, has nearly equal rise and fall time and equal output high-to-low and low-to-high propagation delay. The channel width of the transistors and the load capacitor value are taken as design parameters. The designed circuit has been implemented at the transistor-level and simulated using TSPICE for 45 nm process technology. The PSO-generated results have been compared with SPICE results. A very good accuracy has been achieved. In addition, the advantage of the present approach over an existing approach for the same purpose has been demonstrated through simulation results.

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Efficient nanoscale VLSI standard cell library characterization using a novel delay model

Cited by 15 publications

References 2 publications

Efficient static D-latch standard cell characterization using a novel setup time model

Efficient static D-latch standard cell characterization using a novel setup time model

New voltage and temperature scalable gate delay model applied to a 14nm technology

Modeling and Design of a Nano Scale CMOS Inverter for Symmetric Switching Characteristics

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