Efficient On-line Hardware/Software Task Scheduling for Dynamic Run-time Reconfigurable Systems

Abstract

Modern reconfigurable devices such as FPGAs can be reconfigured at run time. Some of them can be dynamically partially reconfigured, which means part of the FPGA is changed without interrupting other parts. This feature adds tremendous flexibility to the Reconfigurable Computing (RC) Field but also introduces challenges. Reconfigurable Operating Systems tend to ease applications development and most importantly applications verifications and maintenance. In this paper we propose novel scheduling algorithms for reconfigurable computing that can handle both hardware and software tasks. The algorithms proposed reuse hardware tasks to reduce reconfiguration overhead, migrate tasks between software/hardware, and give priority to hardware tasks. Results obtained indicate that adding a software processor element not only adds flexibility, but also increases system performance. Two on-line schedulers were designed and implemented. RCSched-I is a simple based implementation that nominates the first available free Partial Reconfigurable Region (PRR) for new tasks. RCSched-II on the other hand nominates any free PRR. Both schedulers check the nominated PRR(s) against the ready task for a match, then decide if there is a need for reconfiguration or not. RCSched-II reconfigures the least recently configured PRR, which increases hardware tasks reuse and decreases total processing time.

Formalization of the concept of adaptive tasks mapping in the reconfigurable computers on FPGA

“…The widely used method is the embedding of different overheads reducing methods into the known algorithms of tasks scheduling and distribution. Thus, in [12] the method of computational resources reuse in the dynamically reconfigurable computers in the Run Time mode is described. In [2,18], the methods of reconfigurable computational resources placement based on the beforehand reconfiguration are proposed.…”

“…So, the algorithm mapping into the reconfigurable environment at the operating system level complicates substantially the consideration of the FPGA gate parameters and it has the redundant time and performance costs [17]. Besides, a set of papers in this direction [12,18] does not take into account the problem of the FPGA hardware limitations.…”

“…Such methods are the FPGA computational space defragmentation, described in [12,19], the schemes of upsets of task processing [20] and releasing the non-critical configurations, which are considered in [19,21]. These methods are effective ones in the statically reconfigurable computers as well.…”

“…Each M-function at the nodes of the M-graph corresponds to a task that is a definite monatomic process of the computation. Each task is put into hardware task compliance (HW task), which is determined by the vector [12] { , | ( ), , },…”

“…In contrast to the static reconfiguration [9,10], the dynamical reconfiguration is a precondition for the creation of the computing structures, adapted to the requirements of Run Time mode tasks solution [3,[11][12][13]. Firstly, this allows to overcome the limitations of the firm architecture of the high-speed multipurpose computer systems and to approach the real processing performance to the declared …”