Efficient page caching algorithm with prediction and migration for a hybrid main memory

Abstract

Emerging next generation memories, NVRAMs, such as Phase-change RAM (PRAM), Ferroelectric RAM (FRAM), and Magnetic RAM (MRAM) are rapidly becoming promising candidates for large scale main memory because of their high density and low power consumption. Many researchers have attempted to construct a main memory with NVRAMs, in order to make up for the limits of NVRAMs. However, we find that the preexisting page caching algorithms, such as LRU, LIRS, and CLOCK-Pro, are often sub-optimal for NVRAMs due to its DRAM-oriented design including uniform access latency and unlimited endurance. Consequently, the algorithms cannot be directly adapted to the hybrid main memory architecture with PRAM. To mitigate this design limitation, we propose a new page caching algorithm for the hybrid main memory. It is designed to overcome the long latency and low endurance of PRAM. On the basis of the LRU replacement algorithm, we propose a prediction of page access pattern and migration schemes to maintain write-bound access pages to DRAM. The experiment results have convinced us that our page caching algorithm minimizes the number of the write access of PRAM while maintaining the cache hit ratio. The results show that we can reduce the total write access count by a maximum of 52.9% and the consumed energy by 19.9%. Therefore, we can enhance the average page cache performance and reduce the endurance problem in the hybrid main memory.

A Survey on Phase Change Memory-Aware Cache Management

“…Seok et al [56] proposed an LRU-based page management algorithm for hybrid main memory (thereinafter the algorithm is called MIG). MIG adopts a prediction mechanism to identify read-intensive pages and write-intensive pages according to pages' access pattern, and a page migration mechanism to migrate read-intensive pages to PCM and write-intensive pages to DRAM.…”

LDF-CLOCK: The Least-Dirty-First CLOCK Replacement Policy for PCM-based Swap Devices

“…They also consider the balance of PCM write queues in the design of replacement algorithms. Seok et al predicts page access patterns and tries to migrate read-intensive pages to PCM and write-intensive pages to DRAM [10]. For prediction of the read and write access pattern, they calculate the weighting value using the ratio of writes to total references.…”

M-Clock

“…Seok et al [10] proposed a page replacement algorithm to reduce the write count of PRAM in hybrid memory architecture. Their scheme logically partitions the main memory into four regions: DRAM read, DRAM write, PRAM read, and PRAM write.…”

“…Not surprisingly, researchers have suggested various approaches to mitigate the above weaknesses of PCM [1,3,5,7,9,10,13]. Most of the works focused on reducing the number of PCM writes that are crucially concerned with the performance of hybrid memory architecture due to asymmetric read/write latency and limited lifespan of PCM.…”

“…Although these approaches efficiently reduce the number of PCM writes, they also incur performance degradation because they should check both DRAM and PCM when the page to be referenced does not exist in DRAM write-buffer. Meanwhile, other studies proposed some page replacement algorithms for hybrid memory architecture [1,5,7,10]. To reduce the number of PCM writes, their schemes allocate pages to DRAM or PCM after classifying them into writeintensive ones and read-intensive ones.…”