Efficient parallel architecture for implementation of the CMA adaptive antenna

Abstract

This paper presents an efficient parallel architecture for implementation of a constant modulus algorithm (CMA) adaptive array antenna. By inserting delay units into the original CMA, a novel delayed CMA (DCMA) that can significantly reduce the associated critical path is derived. Consequently, a pipelining architecture that supports parallel processing is introduced for implementation of the DCMA. In addition to the pipelining technique, a power-of-two multiplier is proposed for the DCMA leading to the efficient FPGA implementation. The effects of delays and finite word-length on the convergence property of CMA are investigated via simulations. Moreover, the synthesized results demonstrate that FPGA implementation of the proposed architecture using power-of-two arithmetic achieves 26.9% resource reduction in comparison with that of fixed-point arithmetic and operating clock frequency higher than 65 MHz. The implemented FPGA was tested to confirm that the designed architecture operates well for CMA.

Miniaturization of a CPW-fed Dual-Band Antenna for GSM 1800/1900 and WLAN 5 GHz Applications

“…To meet the expectations of the end user, and to make the device more compact and stylish, the external antenna was replaced with a miniaturized internal antenna. A wireless device must support applications like mobile communication, high-speed data communication, and tracking systems, but designing such antennas faces great challenges because of the confined space available inside the devices [1,2]. Different techniques have been proposed for designing dual-band WLAN antennas [3][4][5][6].…”