Efficient Pathfinding Co-Processors for FPGAs

Nery, Alexandre S.; Sena, Alexandre C.; Guedes, Leandro Soares

doi:10.1109/sbac-padw.2017.25

Cited by 2 publications

(3 citation statements)

References 14 publications

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“…Idris [27] proposed the hardware architecture of accelerator for A * algorithm but did not provide simulation result. Nery et al [28] provided the coprocessor design based on Xilinx High-Level Synthesis (HLS) compiler and achieved 2.16x speedup for A * algorithm. However, they did not tackle the bottleneck problem of sorting OPEN list.…”

Section: Fpga Implementation Of Path-planning Algorithmsmentioning

confidence: 99%

“…Yap et al [20] proposed block A * algorithm and achieved up to 4.7x speedup. Nery et al [28] provided the hardware implementation based on Xilinx High-Level Synthesis (HLS) compiler and achieved 2.16x speedup. e comparison results are summarized in Table 6.…”

Section: Comparisonmentioning

confidence: 99%

“…e proposed architecture achieves great performance enhancement compared to the previous work due to the carefully designed OPEN list array and nodes cache. Nery et al's work [28] is also implemented in FPGA, but the execution process is still in serial. erefore, their work's enhancement is not so obvious.…”

Section: Comparisonmentioning

confidence: 99%

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FPGA Implementation of A∗ Algorithm for Real-Time Path Planning

Zhou

Jin

Wang

2020

International Journal of Reconfigurable Computing

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The traditional A∗ algorithm is time-consuming due to a large number of iteration operations to calculate the evaluation function and sort the OPEN list. To achieve real-time path-planning performance, a hardware accelerator’s architecture called A∗ accelerator has been designed and implemented in field programmable gate array (FPGA). The specially designed 8-port cache and OPEN list array are introduced to tackle the calculation bottleneck. The system-on-a-chip (SOC) design is implemented in Xilinx Kintex-7 FPGA to evaluate A∗ accelerator. Experiments show that the hardware accelerator achieves 37–75 times performance enhancement relative to software implementation. It is suitable for real-time path-planning applications.

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Section: Fpga Implementation Of Path-planning Algorithmsmentioning

confidence: 99%

Section: Comparisonmentioning

confidence: 99%