Efficient PC-FPGA Communication over Gigabit Ethernet

Alachiotis, Nikolaos; Berger, Simon; Stamatakis, Alexandros

doi:10.1109/cit.2010.302

Cited by 41 publications

(17 citation statements)

References 8 publications

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“…In addition to implementing this novel algorithm, our hardware implementation is also unique because we deploy the UDP-IP protocol over standard gigabit ethernet for PC-FPGA communication [21]. This allows for a seamless integration of the FPGA accelerator for the alignment kernel with the PaPaRa algorithm running on a standard Linux PC.…”

Section: Related Workmentioning

confidence: 99%

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Accelerating Phylogeny-Aware Short DNA Read Alignment with FPGAs

Alachiotis

Berger

Stamatakis

2011

2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines

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Abstract-Recent advances in molecular sequencing technology have given rise to novel algorithms for simultaneously aligning short sequence reads to reference sequence alignments and corresponding evolutionary reference trees. We present a complete hardware/software implementation for the acceleration of a program called PaPaRa, a newly introduced dynamic programming algorithm for this purpose.We verify the correctness of the proposed architecture on a real FPGA and introduce a straight-forward communication protocol (using gigabit ethernet) for seamless integration with the encapsulating steering software that is executed on a PC processor. The hardware description and the software implementation are freely available for download.When mapped to a Virtex 6 FPGA, our reconfigurable architecture can compute 133.4 billion cell updates per second for the novel, tree-based alignment kernel of PaPaRa. Compared to PaPaRa, running on a 3.2GHz Intel Core i5 CPU, we obtain speedups for the alignment kernel, that range between 170 and 471. For the entire application, that is, the alignment kernel and the trace-back step, we obtain speedups between 74 and 118.

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Section: Related Workmentioning

confidence: 99%

“…For this purpose, a Dell Latitude E4300 series laptop with an Intel Core2 Duo P9400 processor (2.4GHz, Ubuntu) was used. The communication between the FPGA board and the PC was established over Gigabit Ethernet using a dedicated UDP/IP core for direct PC-FPGA communication [21]. Figure 5 illustrates the complete system.…”

Section: B Fpga-based Accelerator Systemmentioning

confidence: 99%

Accelerating Phylogeny-Aware Short DNA Read Alignment with FPGAs

Alachiotis

Berger

Stamatakis

2011

2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines

Self Cite

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“…The resource utilization for UDP/IP stack is provided in Table. II and it is compared to that of previous works. Also, in [31][32][33][34][35][36], the design of a network stack is provided; however, they are incomparable with the present work as the design objectives are not the same. The resource utilization for the proposed method is based on the output of PAR.…”

Section: Experimental Setup and Resultsmentioning

confidence: 51%

A Low Cost High Speed FPGA-Based Image Processing Framework

Mahmoodi

Sayedi

2016

IJMECS

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Abstract-In this paper, a high-speed and low-cost image processing framework based on MATLAB-FPGA interface is proposed that can be used in researches aiming at developing wide variety of not only image processing tasks but also many signal processing applications. In addition, this new framework could be exploited for several other tasks such as on-chip verification, using PC as an enormous external RAM for FPGA while preserving high speed data access, developing hardware-software co-designs, etc. The communication between FPGA and MATLAB is via 1Gbs Ethernet based on UDP/IP protocol which is very promising for high speed data transmission in point-topoint communications. UDP stack is efficiently designed in FPGA based on a fully pipelined architecture with minimum level of logic in order to reach high performance.. Dynamic data transmission between the UDP stack, memory and an arbitrary image processing module makes it possible to practically simulate, debug and implement most relevant applications. The hardware system is relatively low-cost and it consumes a negligible area of a Spartan-6 LXT45 Xilinx FPGA. Operating at 1 Gb/s, theoretically, the system is capable of processing 132 frames of 640*480 color images in a second. The effectiveness of the system is evaluated by means of both place and route simulation and practical implementation of a skin detection algorithm and a motion detector.

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“…We used the C interface of our open-source PC ↔ FPGA communication platform [20] available at http://opencores.org/project,pc fpga com to transfer bit-encoded DNA sequences and issue 13-byte long NV/EV commands to the board. On the FPGA side, the DNA sequences were used to initialize the TIP MEM-ORY, and the NV/EV commands to trigger computations.…”

Section: B Pc-fpga Prototype Systemmentioning

confidence: 99%

FPGA Acceleration of the Phylogenetic Parsimony Kernel?

Alachiotis

Stamatakis

2011

2011 21st International Conference on Field Programmable Logic and Applications

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Abstract-The phylogenetic parsimony function is a popular, discrete criterion for reconstructing evolutionary trees based on molecular sequence data. Parsimony strives to find the phylogenetic tree that explains the evolutionary history of organisms by the least number of mutations. Because parsimony is a discrete function, it should fit well to FPGAs. We present a versatile FPGA implementation of the parsimony function and compare its performance to a highly optimized SSE3-and AVX-vectorized software implementation. We find that, because of a particular constellation in our lab, the speedups that can be achieved by using an FPGA, are substantially less impressive, than usually reported in papers on FPGA acceleration of bioinformatics kernels. We conclude that, a competitive spirit between SW and HW application developers can contribute toward obtaining more objective performance comparisons.

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Efficient PC-FPGA Communication over Gigabit Ethernet

Cited by 41 publications

References 8 publications

Accelerating Phylogeny-Aware Short DNA Read Alignment with FPGAs

Accelerating Phylogeny-Aware Short DNA Read Alignment with FPGAs

A Low Cost High Speed FPGA-Based Image Processing Framework

FPGA Acceleration of the Phylogenetic Parsimony Kernel?

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