Efficient persist barriers for multicores

Linearizability of Persistent Memory Objects Under a Full-System-Crash Failure Model

“…Unfortunately, implicit write-back of persistent memory is difficult to implement in real hardware [9,21,25]. Instead, manufacturers have introduced explicit persistent write-back (pwb) instructions [2,19].…”

“…We generalize proposed implicit persistency models [9,21,25] and real world (explicit) persistency ISAs [2,19] to define our own, new model, which we call explicit epoch persistency. Like real-world explicit ISAs, our persistency model requires programmers to use a pwb to force back data into persistence.…”

“…We assume that persists to a given location respect coherence: the programmer need never worry that a newly persisted value will later be overwritten by the write-back of some earlier value. Unlike prior art, which assumes sequential consistency [25] or total store order [9,21,22], we integrate our instructions into a relaxed (release consistent) model. Table 1 summarizes the mapping of our persistence instructions to the x86 and ARM ISAs.…”

“…Existing persistency models assume that hardware will track dependencies and automatically write dirty cache lines back to NVM as necessary [9,21,25]. Unfortunately, real-world ISAs require the programmer to request writes-back explicitly [2,19].…”

“…Unfortunately, real-world ISAs require the programmer to request writes-back explicitly [2,19]. Furthermore, existing persistency models have been explored only for sequentially consistent (SC) [25] or total-store order (TSO) machines [9,21]. At the same time, recent persistency models [21,25] envision functionality not yet supported by commercial ISAs-namely, hardware buffering in an ordered queue of writes-back to persistent memory, allowing persistence fence (pfence) ordering instructions to complete without waiting for confirmation from the physical memory device.…”