Efficient Phase Unwrapping Architecture for Digital Holographic Microscopy

Abstract

This paper presents a novel phase unwrapping architecture for accelerating the computational speed of digital holographic microscopy (DHM). A fast Fourier transform (FFT) based phase unwrapping algorithm providing a minimum squared error solution is adopted for hardware implementation because of its simplicity and robustness to noise. The proposed architecture is realized in a pipeline fashion to maximize throughput of the computation. Moreover, the number of hardware multipliers and dividers are minimized to reduce the hardware costs. The proposed architecture is used as a custom user logic in a system on programmable chip (SOPC) for physical performance measurement. Experimental results reveal that the proposed architecture is effective for expediting the computational speed while consuming low hardware resources for designing an embedded DHM system.

Region-referenced phase unwrapping architecture for digital holographic microscopy

“…Therefore, it may not perform well for objects with high complexity. In our experiments, the architecture in [17] is not able to correctly unwrap the microlens array shown in Fig. 10(b).…”

“…It can be observed from Table 4 that the proposed architecture has significantly lower area costs. The consumption of ALMs and embedded memory bits are only 4.52% (i.e., 960 versus 21,212) and 58.77% (i.e., 2,923,940 versus 4,975,122), respectively, of those of the architecture presented in [17]. Moreover, the proposed architecture does not utilize any DSP blocks.…”

“…The architecture in [17] performs phase unwrapping by the FFT-based noniterative algorithm [10]. It therefore has faster computation time as compared with that of the proposed architecture, whose phaseunwrapping operations are iterative.…”

“…Moreover, the proposed architecture does not utilize any DSP blocks. On the contrary, 40 DSP blocks are used in the architecture in [17]. The small area costs utilized by the proposed architecture are beneficial for lowering the costs of the entire embedded system for applications such as mobile DHMs [18].…”

“…Moreover, some of these implementations are based on GPU, which may be difficult to use for embedded devices due to high hardware cost and power consumption. Although the FPGA implementation [17] of the noniterative algorithm [10] may have higher throughput due to lower number of memory accesses, the area costs of the implementation are high. It therefore may not be suited for embedded DHM applications [18] with limited hardware resources.…”