Efficient power macromodeling technique for conventional MOS transistors

Abstract

Abstract─ In this paper, we propose a new power macromodeling technique for the power estimation of conventional metal-oxide-semiconductor (MOS) transistors. As the dynamic power is directly linked with the load capacitance (C L ), it is also a lumped capacitance of all internal parasitic capacitances. In our model, we take an account of the parasitic capacitances with their dependence on channel width and the length. Suitable values of other factors (i.e. threshold voltage V T , gate voltage V GS , drain voltage V DD etc.) are used for the power consumption of the MOS transistors. The Preliminary results are effective and our macromodel provides the accurate power estimation.