Efficient Processing of Convolutional Neural Networks on SW26010

Abstract

Artificial intelligence has developed rapidly in recent years. Deep neural networks are the basis of many artificial intelligence applications. How to accelerate the computational processing of deep neural networks is very important. To explor the potential for accelerating the process deep neural networks on various hardware platforms, we propose a convolutional neural network optimization method based on the Weight-Stationary for SW26010 processor. We re-circulate convolution loops and use hybrid DMA transmission mode to increase memory bandwidth and reduce memory access overhead. On top of those, further optimizations are done based on register communication, asynchronous DMA transfer double buffering, instruction scheduling and other schemes. Finally, we achieve a double-precision convolution performance over 2.4 Tflops, achieving 81% of the processor's peak performance. In multiple parameters, we achieve a proforamnce acceleration of 2.4 − 4.0× speedup compared to the Tesla K80 GPU with cuDNNv7.

Runtime Adaptive Matrix Multiplication for the SW26010 Many-Core Processor

“…To obtain higher peak performance, modern processors not only integrate more and more cores, but also widely apply superscalar technology [29]. Many studies [11], [13], [30], [31] have focused on instruction-level optimization methods based on superscalar technology. The same is true of the SW26010 processor, which has two pipelines (P0 and P1) on one CPE.…”

“…The execution time of CNNs becomes long and unacceptable as larger data sets and more complex CNNs emerge. Because convolution accounts for more than 90% of the total computation in CNNs [2], highly efficient convolution algorithms on many-core processors have become a popular research direction in academia and industry.…”

“…Many studies are devoted to improving the performance of convolution on GPUs [3,4] and CPUs [5,6], which has promoted the perfection of deep neural network libraries such as NVIDIA cuDNN [7] and Intel MKL-DNN [8]. Furthermore, the acceleration of convolution algorithms on other hardware platforms also attracts researchers to participate, such as Cambrian's DianNao series [9], Google's TPU [10], and SW26010 [2]. As the main contributor to the computational power of the world-class Sunway TaihuLight supercomputer, SW26010 [11] has several special architectural features such as user-controllable memory hierarchy, asynchronous direct memory access (DMA), on-chip regis-ter communication, and double-pipeline instruction execution.…”

“…However, the current support of convolution on SW26010 is still rudimentary. The existing studies [2,12,13] deploy optimization methods by simply mapping convolution tasks into the whole CG (core group). They continually enhance the runtime peak performance of algorithms but rarely consider the adaptability for changeable convolution scenes.…”

Attention‐based hierarchical pyramid feature fusion structure for efficient face recognition

“…ShuffleFaceNet [11] is adapted from the efficient network ShuffleNetV2 [12], and similar to MobileFaceNet, global depth-wise convolution is used to output the facial feature vector. Based on the variable group convolutional proposed in VarGNet [13], VarGFaceNet [14] designed a compact yet high-accurate FR model. Using recursive knowledge distillation, VarGFaceNet [14] achieved 99.85% accuracy on the LFW benchmark and obtained the best results for the ICCV 2019 LFR challenge DeepGlint-Light track [7].…”