Efficient RNS Scalers for the Extended Three-Moduli Set $(2^{n}-1, 2^{n+p}, 2^{n}+1)$

Hiasat, A.A.

doi:10.1109/tc.2017.2652474

Cited by 21 publications

(32 citation statements)

References 27 publications

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“…Also, modeling was done to compare the proposed moduli sets with balanced RNS moduli sets. The following types of moduli sets were chosen for the simulation: {2 n − 1, 2 n , 2 n + 1} [29,30], 2 n − 1, 2 n+k , 2 n + 1 [31], 2 n − 1, 2 n , 2 n + 1, 2 n+1 + 1 [34], 2 n − 1, 2 n + 1, 2 n±1 − 1, 2 n+k [35]. All simulated circuits were described in very high speed integrated circuit (VHSIC) hardware description language (VHDL).…”

Section: Resultsmentioning

confidence: 99%

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Construction of Residue Number System Using Hardware Efficient Diagonal Function

et al. 2019

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The residue number system (RNS) is a non-positional number system that allows one to perform addition and multiplication operations fast and in parallel. However, because the RNS is a non-positional number system, magnitude comparison of numbers in RNS form is impossible, so a division operation and an operation of reverse conversion into a positional form containing magnitude comparison operations are impossible too. Therefore, RNS has disadvantages in that some operations in RNS, such as reverse conversion into positional form, magnitude comparison, and division of numbers are problematic. One of the approaches to solve this problem is using the diagonal function (DF). In this paper, we propose a method of RNS construction with a convenient form of DF, which leads to the calculations modulo 2 n , 2 n − 1 or 2 n + 1 and allows us to design efficient hardware implementations. We constructed a hardware simulation of magnitude comparison and reverse conversion into a positional form using RNS with different moduli sets constructed by our proposed method, and used different approaches to perform magnitude comparison and reverse conversion: DF, Chinese remainder theorem (CRT) and CRT with fractional values (CRTf). Hardware modeling was performed on Xilinx Artix 7 xc7a200tfbg484-2 in Vivado 2016.3 and the strategy of synthesis was highly area optimized. The hardware simulation of magnitude comparison shows that, for three moduli, the proposed method allows us to reduce hardware resources by 5.98-49.72% in comparison with known methods. For the four moduli, the proposed method reduces delay by 4.92-21.95% and hardware costs by twice as much by comparison to known methods. A comparison of simulation results from the proposed moduli sets and balanced moduli sets shows that the use of these proposed moduli sets allows up to twice the reduction in circuit delay, although, in several cases, it requires more hardware resources than balanced moduli sets. such as field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC). All these attractive features increase interest to RNS in the areas where large amounts of computation are needed. The applications of RNS are digital signal processing [2][3][4], cryptography [5][6][7], digital image processing [8], cloud computing [9], Internet of Things [10] and others. In [11], the authors propose a technique to estimate real-valued numbers by means of the Chinese remainder theorem (CRT), employing for this goal a Kroenecker based M-Estimation, to improve robustness. A new method based on the Chinese remainder theorem (CRT) is proposed for absolute position computation in [12]. This has advantages in terms of hardware and flexibility because it does not use memory. The authors of [13] offer to use RNS to improve the performance of the convolutional neural network developed for pattern recognition tasks. Reference [14] describes the method of construction for finite impulse response filers using RNS.However, the limitations of RNS include some operations such a...

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Section: Resultsmentioning

confidence: 99%

“…{2 n − 1, 2 n , 2 n + 1} [29,30] 2 n − 1, 2 n+p , 2 n + 1 [31] 2 2n+p , 2 2n − 1, 2 2n + 1 n odd, p ≤ n−5…”

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Construction of Residue Number System Using Hardware Efficient Diagonal Function

et al. 2019

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“…There is no scaler published in the literature for the moduli set {2 n+1 − 1, 2 n , 2 n − 1}. The new proposed scaler was compared with the most recent and efficient published scaler of the traditional moduli set {2 n + 1, 2 n , 2 n − 1} [12,13]. The unit-gate model was used as a basis for theoretical comparison [14].…”

Section: Comparison and Vlsi Realizationmentioning

confidence: 99%

“…However, the area and delay of the (2 p + 1) modular adder are 4.5p log 2 p + 0.5p + 6 and 2 log 2 p + 3 , respectively [20]. Table 1 lists the area and time delay requirements of the proposed scaler and those in [12,13]. Table 1.…”

Section: Comparison and Vlsi Realizationmentioning

confidence: 99%

“…The work that has been published so far regarding scaling the RNS deals either with moduli sets of general form or with the traditional set. The main scalers that deal specifically with the traditional moduli set M 2 = {2 n + 1, 2 n , 2 n − 1} are presented in [7][8][9][10][11][12][13]. Those that are most efficient in terms of different metrics are presented in [12,13].…”

Section: Introductionmentioning

confidence: 99%

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New Residue Number System Scaler for the Three-Moduli Set {2n+1 − 1, 2n, 2n − 1}

Hiasat

2018

Computers

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This work proposes the first scaler designed specifically for the three-moduli set M 1 = { 2 n + 1 − 1 , 2 n , 2 n − 1 } . Hence, there is no other functionally similar scaler to compare the proposed scaler with. However, when compared with the latest published scalers for a different moduli set, M 2 = { 2 n + 1 , 2 n , 2 n − 1 } , the proposed scaler has a better area and power performance, while it requires a longer time delay. As demonstrated in earlier publications, replacing the ( 2 n + 1 ) channel in the M 2 moduli set by the ( 2 n + 1 − 1 ) channel, to form the M 1 moduli set, considerably improves the overall time performance of residue-based multiply–accumulate arithmetic units.

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General Frameworks for Designing Arithmetic Components for Residue Number Systems

Hiasat

2020

Advances in Intelligent Systems and Computing

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Efficient RNS Scalers for the Extended Three-Moduli Set $(2^{n}-1, 2^{n+p}, 2^{n}+1)$

Cited by 21 publications

References 27 publications

Construction of Residue Number System Using Hardware Efficient Diagonal Function

Construction of Residue Number System Using Hardware Efficient Diagonal Function

New Residue Number System Scaler for the Three-Moduli Set {2n+1 − 1, 2n, 2n − 1}

General Frameworks for Designing Arithmetic Components for Residue Number Systems

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