Efficient RTL power estimation for large designs

Abstract

The adoption of register-transfer level (RTL) sign-off in ASIC design methodologies, and the increasing scale of system-on-chip integration, are leading to unprecedented accuracy and efficiency demands on RT-level estimation tools. In this work, we focus on the deployment of a simulation-based RTL power estimation tool in a commercial design flow, and describe several enhancements that improve its efficiency and scalability for large, industrial designs. We profile the computational effort involved in RTL power estimation, and propose a suite of acceleration techniques, including (i) transformation of the enhanced RTL description (functional model with annotations for power estimation) to be more simulatorfriendly, (ii) computation vs. storage tradeoffs, and (iii) a novel variation of statistical sampling, called partitioned sampling. Our techniques result in an optimized allocation of the overall computational effort for power estimation and minimize the computational effort involved in the evaluation of power models.Extensive experimental results in the context of a commercial design flow have yielded promising results (e.g., upto 31X reduction in power estimation time with negligible loss of accuracy) on industrial designs of upto 1.25 million transistors. In addition to accurate power estimation for an entire circuit, these acceleration techniques result in superior accuracy of local power estimates for individual components or small sub-circuits, compared to conventional sampling or test-bench compaction techniques.

Modeling and Estimation for the Power Consumption of Matrix Computation on Multi-core Platform

“…In general, the power consumption can be estimated at different levels of abstraction, such as: simulating the circuit at the transistor or switch level; modeling the middle-grained components, i.e. adders, multipliers, and registers; [1] modeling the functional or algorithmic behaviors of hardware components [2] and etc. In lower level models the available physical information allows obtaining accurate power estimates, on the other side, higher level models are depending on the abstraction in describing hardware systems, they use more indirect and approximate design parameters.…”

Hardware Accelerated Power Estimation

“…In our experimental setup, we begin with a C behavioral description of a design and run a commercial behavioral synthesis tool [10] to synthesize an RTL description. We perform RTL power estimation using (a) PowerTheater [1], and (b) an internal power estimation tool developed at NEC [2]. RTL power estimates and power emulation results are obtained for NEC's CB130M [11] 0:13µ standard cell based technology.…”

“…To explain the structure of hardware power models, we consider a cycle-accurate linear regression based macromodel [8], which expresses the power consumed in an RTL component with n input/output bits as ∑ A circuit description that has been enhanced with power estimation hardware lends itself to simulation using any HDL simulator [2], or emulation using a hardware prototyping platform as suggested in this work. Figure 2 illustrates the overall flow for power emulation.…”

“…However, efficient power estimation for large designs remains a challenge due to increases in design and testbench complexity. For example, RTL power estimation for a 1.25 million transistor MPEG4 decoder circuit (for an input stimulus containing 4 frames of a video stream) required 43 minutes and 55 minutes to run on two different state-of-the-art commercial tools [1,2]. Power estimation tools that operate at the transistor and gate levels are known to be much (10X to 100X) slower.…”

PowerViP: SoC power estimation framework at transaction level

“…The estimation accuracy becomes even lower when we employ an analytical method. Therefore, significant amount of work has been done on RTL macro modeling of IP power consumption [17]. Although the procedure to build an RTL power macro model is clear, it is still difficult to automate the process.…”