Efficient Scheduling, Mapping and Memory Bandwidth Allocation for Safety-Critical Systems

Dugo, Alexy Torres Aurora; Lefoul, Jean-Baptiste; Ben-Salem, Aymen; Harnois, Serge; Magalhães, Felipe Göhring de; Nicolescu, Gabriela

doi:10.1109/newcas52662.2022.9842219

Cited by 1 publication

(1 citation statement)

References 13 publications

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“…As demonstrated in practice, Moore’s law validated the theory of continuous scaling and miniaturization of transistors in an integrated circuit (IC). This theory, along with the concept of abstraction, has guided the semiconductor industry to the present day leading to the emergence of System on Chip (SoC), hybrid scheduling ( Ghavidel, Sedaghat & Naghibzadeh, 2020 ; Aurora Dugo et al, 2022 ), heterogeneous multicore processors ( Pei, Kim & Gaudiot, 2016a ; Krishnakumar et al, 2020 ), and hardware microkernels ( Dantas, De Azevedo & Gimenez, 2019a ), today’s computing systems ( Bae, 2021 ) and Internet of Things (IoT) concepts. With technological development, designers of central processing units have developed modern IC in various forms such as FPGAs ( Li et al, 2022 ), complex programmable logic devices (CPLDs), or application-specific integrated circuits (ASICs), which are faster and smaller, consume less power and, last but not least, are cheaper.…”

Section: Introductionmentioning

confidence: 99%

Soft-core processor integration based on different instruction set architectures and field programmable gate array custom datapath implementation

Zagan

Găitan

2023

PeerJ Computer Science

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One of the fundamental requirements of a real-time system (RTS) is the need to guarantee re-al-time determinism for critical tasks. Task execution rates, operating system (OS) overhead, and task context switching times are just a few of the parameters that can cause jitter and missed deadlines in RTS with soft schedulers. Control systems that are susceptible to jitter can be used in the control of HARD RTS as long as the cumulative value of periodicity deviation and worst-case response time is less than the response time required by that application. This artcle presents field-programmable gate array (FPGA) soft-core processors integration based on different instruction set architectures (ISA), custom central processing unit (CPU) datapath, dedicated hardware thread context, and hardware real-time operating system (RTOS) implementations. Based on existing work problems, one parameter that can negatively influence the performance of an RTS is the additional costs due to the operating system. The scheduling and thread context switching operations can significantly degrade the programming limit for RTS, where the task switching frequency is high. In parallel with the improvement of software scheduling algorithms, their implementation in hardware has been proposed and validated to relieve the processor of scheduling overhead and reduce RTOS-specific overhead.

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