Efficient seed utilization for reseeding based compression [logic testing]

Volkerink, E.; Mitra, Subhasish

doi:10.1109/vtest.2003.1197656

Cited by 51 publications

(30 citation statements)

References 22 publications

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“…An efficient LFSR reseeding technique is proposed in [20]. It allows the generation of a single scan slice from multiple seeds, or multiple scan slices from a single seed.…”

Section: Proposed Approachmentioning

confidence: 99%

“…An additional tester channel is needed to control when reseeding occurs. In this paper, without loss of generality, we choose to use the compression technique of [20] because of its high encoding efficiency. The proposed test-scheduling method can also be used with other linear-decompression-based compression techniques [22], [23].…”

Section: Proposed Approachmentioning

confidence: 99%

“…By carefully designing the TAM and test wrappers, together with proper test scheduling, an equivalent core can be obtained whose testing time is minimized. Thereafter, the LFSR reseeding technique of [20] is applied for the equivalent core. TAT is significantly reduced because: 1) multiple cores are tested in parallel and 2) when some cores are in the capture or inactive mode, other cores are in the shift mode and receiving data from the LFSR.…”

Section: B Equivalent Corementioning

confidence: 99%

“…We choose the LFSR reseeding technique proposed in [20] as the compression engine because of its high encoding efficiency. A single on-chip LFSR-based decompressor is used to feed all cores on the SOC.…”

mentioning

confidence: 99%

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Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip

Wang

Chakrabarty

Wang³

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-We present a system-on-chip (SOC) testing approach that integrates test data compression, test-access mechanism/test wrapper design, and test scheduling. An efficient linear feedback shift register (LFSR) reseeding technique is used as the compression engine. All cores on the SOC share a single on-chip LFSR. At any clock cycle, one or more cores can simultaneously receive data from the LFSR. Seeds for the LFSR are computed from the care bits for the test cubes for multiple cores. We also propose a scan-slice-based scheduling algorithm that attempts to maximize the number of care bits the LFSR can produce at each clock cycle, such that the overall test application time (TAT) is minimized. This scheduling method is static in nature because it requires predetermined test cubes. We also present a dynamic scheduling method that performs test compression during test generation. Experimental results for International Symposium on Circuits and Systems and International Workshop on Logic and Synthesis benchmark circuits, as well as industrial circuits, show that optimum TAT, which is determined by the largest core, can often be achieved by the static method. If structural information is available for the cores, the dynamic method is more flexible, particularly since the performance of the static compression method depends on the nature of the predetermined test cubes.

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“…An efficient LFSR reseeding technique is proposed in [20]. It allows the generation of a single scan slice from multiple seeds, or multiple scan slices from a single seed.…”

Section: Proposed Approachmentioning

confidence: 99%

Section: Proposed Approachmentioning

confidence: 99%

Section: B Equivalent Corementioning

confidence: 99%

mentioning

confidence: 99%

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Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip

Wang

Chakrabarty

Wang³

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Other techniques are based on on-chip pattern decompression, such as scan-chain concealment [15], geometric-primitive based compression [16], mutation encoding [17], deterministic embedded test (reusing the scan chain of one core in a SoC to compress the patterns for another core) [18], packet-based compression [19] and LFSR reseeding [2] [20] [21]. An embedded deterministic test technology for low cost test to reduce the scan test data volume and scan test time is presented in [22].…”

Section: Introductionmentioning

confidence: 99%

Nine-coded compression technique with application to reduced pin-count testing and flexible on-chip decompression

Tehranipour¹,

Nourani²,

Chakrabarty³

Proceedings Design, Automation and Test in Europe Conference and Exhibition

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Abstract-This paper presents a new test data compression technique based on a compression code that uses exactly nine codewords. In spite of its simplicity, it provides significant reduction in test data volume and test application time. In addition, the decompression logic is very small and independent of the precomputed test data set. Our technique leaves many don't-care bits unchanged in the compressed test set, and these bits can be filled randomly to detect non-modeled faults. The proposed technique can be efficiently adopted for single-or multiple-scan chain designs to reduce test application time and pin requirement. Experimental results for ISCAS'89 benchmarks illustrate the flexibility and efficiency of the proposed technique.

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Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns

Al-Yamani

McCluskey

2010

J Electron Test

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Efficient seed utilization for reseeding based compression [logic testing]

Cited by 51 publications

References 22 publications

Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip

Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip

Nine-coded compression technique with application to reduced pin-count testing and flexible on-chip decompression

Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns

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