Efficient semisystolic architectures for finite-field arithmetic

Jain, Siddharth; Li, Song; Parhi, Keshab K.

doi:10.1109/92.661252

Cited by 118 publications

(92 citation statements)

References 16 publications

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“…Jain et al proposed semisystolic architectures for parallel squaring in polynomial basis [94]. Information about the complexity of squaring can be found in the works by Wu [214,216].…”

Section: Hardware Implementationsmentioning

confidence: 99%

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Hardware architectures for public key cryptography

et al. 2003

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This paper presents an overview of hardware implementations for the two commonly used types of Public Key Cryptography, i.e. RSA and Elliptic Curve Cryptography (ECC), both based on modular arithmetic. We first discuss the mathematical background and the algorithms to implement these cryptosystems. Next an overview is given of the different hardware architectures which have been proposed in the literature.

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“…Jain et al proposed semisystolic architectures for parallel squaring in polynomial basis [94]. Information about the complexity of squaring can be found in the works by Wu [214,216].…”

Section: Hardware Implementationsmentioning

confidence: 99%

“…13. The other work about this structure is from Jain et al [94]. They also fabricated a multiplier over GF (2 4 ) chip using CMOS 1.2 µm technology.…”

Section: Standard Basesmentioning

confidence: 99%

Hardware architectures for public key cryptography

et al. 2003

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“…As a result, efficient multipliers are important from a system performance point of view. Although several multipliers have been developed with a polynomial basis of GFð2 m Þ, their high space and time complexities are major limitations in cryptographic applications [1,2,3,4]. Thus, further research on efficient multiplication architectures with low space and time complexities is required.…”

Section: Introductionmentioning

confidence: 99%

Efficient systolic modular multiplier/squarer for fast exponentiation over GF(2m)

Choi

Lee

2015

IEICE Electron. Express

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Using the concept of common components, this letter shows that field multiplication and squaring over GF(2 m ) can be efficiently combined, with little hardware overhead. The analysis results show that about 39.23% area-time (AT) complexity is improved when we employ the combined systolic multiplier/squarer instead of implementing the multiplier and the squarer separately in the least significant bit (LSB)-first exponentiation. The proposed architecture features regularity, unidirectional data flow, and local interconnection, and thus is well suited to VLSI implementation.

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“…The reader may refer to [7] for a detailed description of parallel finite field multiplication algorithms. …”

Section: Finite Field Fundamentalsmentioning

confidence: 99%

Low-energy heterogeneous digit-serial Reed-Solomon codecs

Parhi²,

Kuroda³

et al.

Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '98 (Cat. No.98CH36181

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Reed-Solomon (RS) codecs are used for error control coding in many applications such as digital audio, digital TV, software radio, CD players, and wireless and satellite communications. This paper considers software-based implementation of RS codecs where special instructions are assumed to be used to program finite field multiplication datapaths inside a domain-specific programmable digital-signal processor (DS-PDSP). A heterogeneous digit-serial approach is presented, where the heterogeneity corresponds to the use of different digit-sizes in the multiply-accumulate (MAC for polynomial multiplication) and degree reduction (DEGRED for polynomial modulo operation) subarrays. The salient feature of this digit-serial approach is that only the digit-cells are implemented in hardware, the finite field multiplications are performed digit-serially in software by dynamically scheduling the internal digit-level operations in RS encoders and decoders. It is concluded that, for 2-error-correcting RS(n; k) codec implementations over finite field GF2 8 , a parallel MAC unit (of digit-size 8) and a DEGRED unit with digit-size 2 is the best datapath, with respect to least energy consumption and energy-delay products; with this datapath architecture and appropriate digit-serial scheduling strategies, more than 60 energy reduction and more than 1=3 energydelay reduction can be achieved compared with the parallel multiplication datapath based approach.

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Efficient semisystolic architectures for finite-field arithmetic

Cited by 118 publications

References 16 publications

Hardware architectures for public key cryptography

Hardware architectures for public key cryptography

Efficient systolic modular multiplier/squarer for fast exponentiation over <i>GF</i>(2<i><sup>m</sup></i>)

Low-energy heterogeneous digit-serial Reed-Solomon codecs

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