Efficient Systolic-Array Redundancy Architecture for Offline/Online Repair

Abstract

Neural-network computing has revolutionized the field of machine learning. The systolicarray architecture is a widely used architecture for neural-network computing acceleration that was adopted by Google in its Tensor Processing Unit (TPU). To ensure the correct operation of the neural network, the reliability of the systolic-array architecture should be guaranteed. This paper proposes an efficient systolic-array redundancy architecture that is based on systolic-array partitioning and rearranging connections of the systolic-array elements. The proposed architecture allows both offline and online repair with an extended redundancy architecture and programmable fuses and can ensure reliability even in an online situation, for which the previous fault-tolerant schemes have not been considered.

PULP Fiction No More—Dependable PULP Systems for Space

“…General-purpose computing systems might not provide enough performance and efficiency to accelerate specific kernels needed for deep learning execution [37], [38], requiring coupling with application-specific hardware accelerating units. Even though machine learning has some capabilities of resisting faults, reliability in the acceleration of neural networks' execution is still a requirement that makes machine learning accelerators benefit from features that guarantee the reliability of their operation [39].…”

Fault-injection based attacks and countermeasure on deep neural network accelerators

“…Several techniques have been proposed to address permanent and transient faults within systolic arrays, including software-and hardware-based solutions. Hardware-based ap-proaches employ redundant PEs to replace faulty PEs [21]- [24]. These methods assume that faults can be localized during testing, thereby assuming that the precise locations of faults are known [17], [21], [23], [25].…”

“…Hardware-based ap-proaches employ redundant PEs to replace faulty PEs [21]- [24]. These methods assume that faults can be localized during testing, thereby assuming that the precise locations of faults are known [17], [21], [23], [25].…”