2017 IEEE International Conference on Computer Design (ICCD) 2017
DOI: 10.1109/iccd.2017.112
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Efficient Tagged Memory

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Cited by 38 publications
(86 citation statements)
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“…To estimate the runtime in CPU cycles, we map executed instructions to actual CPU cycles using different pipelined CPU models. We first define a simple baseline model, against which we then compare two possible realizations of TIMBER-V, namely TIMBER-V Model A, capturing unoptimized implementations, and TIMBER-V Model [31,45,48]. We outline these CPU models in the following and summarize them in Table V.…”
Section: A Methodologymentioning
confidence: 99%
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“…To estimate the runtime in CPU cycles, we map executed instructions to actual CPU cycles using different pipelined CPU models. We first define a simple baseline model, against which we then compare two possible realizations of TIMBER-V, namely TIMBER-V Model A, capturing unoptimized implementations, and TIMBER-V Model [31,45,48]. We outline these CPU models in the following and summarize them in Table V.…”
Section: A Methodologymentioning
confidence: 99%
“…A tag cache can serve tags in parallel to ordinary memory accesses and thus, hide the tag checking latency for all cached tags. By comparing state-of-the-art literature on tagged memory architectures, we observe that tag caching can reduce the average overhead of tag accesses into the low single digit range [31,45,48]. Considering that our work utilizes two tag bits per word, we conservatively estimate the expected performance impact of the tag operations with 10%, which is reflected in Model B.…”
Section: A Methodologymentioning
confidence: 99%
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“…Then there is a Bluespec [11] FPGA hardware implementation of the architecture, and a software stack above it, adapting LLVM [12] and FreeBSD [13] to CHERI-MIPS. All this has involved extensive work on the interaction between the capability system and systems aspects of memory management (static and dynamic linking, process creation, context switching, page swapping and signal delivery) [14]; on the overhead of compiling pointers to capabilities [5], [15]; on compartmentalisation of legacy software [16]; and on the performance overhead of tagged memory [17] and protectiondomain switches [18]. The underlying ideas are portable, not MIPS-specific, and work is underway on experimental academic RISC-V and industrial Arm versions -the latter in a major project involving Arm and the UK Government [19], [20] to produce prototype silicon and a development board.…”
Section: A the Cheri Contextmentioning
confidence: 99%
“…Dynamic analysis techniques as in [Nethercote and Seward 2007;Rosu et al 2009;Serebryany et al 2012] instrument program executables and report errors as they occur during program execution. Recently, there has also been emerging interest in enforcing runtime memory safety using hardware and software support for tagged memory [Joannou et al 2017;lowRISC 2019;Oleksenko et al 2018;Serebryany et al 2018;Watson et al 2015].…”
Section: Related Workmentioning
confidence: 99%