Efficient traversal of decision tree ensembles with FPGAs

Molina, Romina; Loor, Fernando; Gil-Costa, Verónica; Nardini, Franco Maria; Perego, Raffaele; Trani, Salvatore

doi:10.1016/j.jpdc.2021.04.008

Cited by 7 publications

(4 citation statements)

References 43 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…An example of another line of research is an implementation of a state-of-the-art tree traversal algorithm [30]. They present a system-on-chip (SoC)-based field-programmable gate arrays (FPGAs) implementation of the QuickScorer algorithm [31], which is an efficient tree traversal algorithm designed for large binary tree ensembles.…”

Section: Related Workmentioning

confidence: 99%

Fast and Energy-Efficient Oblique Decision Tree Implementation with Potential Error Detection

Lim

2024

Electronics

View full text Add to dashboard Cite

In the contemporary landscape, with the proliferation of cyber-physical systems and the Internet of Things, intelligent embedded systems have become ubiquitous. These systems derive their intelligence from machine learning algorithms that are integrated within them. Among many machine learning algorithms, decision trees are often favored for implementation in such systems due to their simplicity and commendable classification performance. In this regard, we have proposed the efficient implementations of a fixed-point decision tree tailored for embedded systems. The proposed approach begins by identifying an input vector that might be classified differently by a fixed-point decision tree than by a floating-point decision tree. Upon identification, an error flag is activated, signaling a potential misclassification. This flag serves to bypass or disable the subsequent classification procedures for the identified input vector, thereby conserving energy and reducing classification latency. Subsequently, the input vector is alternatively classified based on class probabilities gathered during the training phase. In comparison with traditional fixed-point implementations, our proposed approach is proven to be 23.9% faster in terms of classification speed, consuming 11.5% less energy without compromising classification accuracy. The proposed implementation, if adopted in a smart embedded device, can provide a more responsive service to its users as well as longer battery life.

show abstract

Section: Related Workmentioning

confidence: 99%

Fast and Energy-Efficient Oblique Decision Tree Implementation with Potential Error Detection

Lim

2024

Electronics

View full text Add to dashboard Cite

show abstract

“…Lucchese et al (2015b) apply these ideas to QuickScorer with different flavors of blocking (Dato et al, 2016), and make further improvements through vectorization over multiple documents (Lucchese et al, 2016b), multi-core and GPU parallelism (Lettich et al, 2019). More recently, Gil-Costa et al (2022) and Molina et al (2021) propose a novel design of of the QuickScorer algorithm and the application of binning or quantization techniques to tree ensembles to fully leverage novel, energy-efficient field-programmable gate arrays (FPGAs). Ye et al (2018) take the data structure in QuickScorer and make it more compact in their algorithm, RapidScorer.…”

Section: Feature-major Traversalmentioning

confidence: 99%

ReNeuIR: Reaching Efficiency in Neural Information Retrieval

Bruch¹,

Lucchese

Nardini

2022

Proceedings of the 45th International ACM SIGIR Conference on Research and Development in Information Retrieval

View full text Add to dashboard Cite

As information retrieval researchers, we not only develop algorithmic solutions to hard problems, but we also insist on a proper, multifaceted evaluation of ideas. The literature on the fundamental topic of retrieval and ranking, for instance, has a rich history of studying the effectiveness of indexes, retrieval algorithms, and complex machine learning rankers, while at the same time quantifying their computational costs, from creation and training to application and inference. This is evidenced, for example, by more than a decade of research on efficient training and inference of large decision forest models in Learning to Rank (LtR). As we move towards even more complex, deep learning models in a wide range of applications, questions on efficiency have once again resurfaced with renewed urgency. Indeed, efficiency is no longer limited to time and space; instead it has found new, challenging dimensions that stretch to resource-, sampleand energy-efficiency with ramifications for researchers, users, and the environment.This monograph takes a step towards promoting the study of efficiency in the era of neural information retrieval by offering a comprehensive survey of the literature on efficiency and effectiveness in ranking, and to a limited extent, retrieval. This monograph was inspired by the parallels that exist between the challenges in neural network-based ranking solutions and their predecessors, decision forest-based LtR models, as well as the connections between the solutions the literature to date has to offer. We believe that by understanding the fundamentals underpinning these algorithmic and data structure solutions for containing the contentious relationship between efficiency and effectiveness, one can better identify future directions and more efficiently determine the merits of ideas. We also present what we believe to be important research directions in the forefront of efficiency and effectiveness in retrieval and ranking.

show abstract

“…As a result, the first input instance in the dataset will be the one with the largest number of non-zero attributes. The algorithm then calculates current_sparse_perc at lines 9-11, prior to entering the inner loop (lines [12][13][14][15][16][17][18]. In this loop, the algorithm starts with a selection of the first input instance from the dataset.…”

Section: Attribute Sparse Training Of Svmmentioning

confidence: 99%

“…A significant effort has been made by the scientific community in this direction. Regarding DTs, a number of FPGA DT implementations were presented in the literature [15][16][17][18][19][20]. These proposed architectures dealt with the acceleration of the axis-parallel, oblique or nonlinear DTs and the ensembles of dense DTs.…”

Section: Introductionmentioning

confidence: 99%

Universal Reconfigurable Hardware Accelerator for Sparse Machine Learning Predictive Models

2022

View full text Add to dashboard Cite

This study presents a universal reconfigurable hardware accelerator for efficient processing of sparse decision trees, artificial neural networks and support vector machines. The main idea is to develop a hardware accelerator that will be able to directly process sparse machine learning models, resulting in shorter inference times and lower power consumption compared to existing solutions. To the author’s best knowledge, this is the first hardware accelerator of this type. Additionally, this is the first accelerator that is capable of processing sparse machine learning models of different types. Besides the hardware accelerator itself, algorithms for induction of sparse decision trees, pruning of support vector machines and artificial neural networks are presented. Such sparse machine learning classifiers are attractive since they require significantly less memory resources for storing model parameters. This results in reduced data movement between the accelerator and the DRAM memory, as well as a reduced number of operations required to process input instances, leading to faster and more energy-efficient processing. This could be of a significant interest in edge-based applications, with severely constrained memory, computation resources and power consumption. The performance of algorithms and the developed hardware accelerator are demonstrated using standard benchmark datasets from the UCI Machine Learning Repository database. The results of the experimental study reveal that the proposed algorithms and presented hardware accelerator are superior when compared to some of the existing solutions. Throughput is increased up to 2 times for decision trees, 2.3 times for support vector machines and 38 times for artificial neural networks. When the processing latency is considered, maximum performance improvement is even higher: up to a 4.4 times reduction for decision trees, a 84.1 times reduction for support vector machines and a 22.2 times reduction for artificial neural networks. Finally, since it is capable of supporting sparse classifiers, the usage of the proposed hardware accelerator leads to a significant reduction in energy spent on DRAM data transfers and a reduction of 50.16% for decision trees, 93.65% for support vector machines and as much as 93.75% for artificial neural networks, respectively.

show abstract

Efficient traversal of decision tree ensembles with FPGAs

Cited by 7 publications

References 43 publications

Fast and Energy-Efficient Oblique Decision Tree Implementation with Potential Error Detection

Fast and Energy-Efficient Oblique Decision Tree Implementation with Potential Error Detection

ReNeuIR: Reaching Efficiency in Neural Information Retrieval

Universal Reconfigurable Hardware Accelerator for Sparse Machine Learning Predictive Models

Contact Info

Product

Resources

About