2007
DOI: 10.1109/tcad.2006.883912
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Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits

Abstract: This paper presents an efficient method for verifying hazard freedom in timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that utilize explicit timing information for optimization throughout the entire design process. In asynchronous circuits, correct operation requires that there are no hazards in the circuit implementation. Therefore, when designing an asynchronous circuit, each internal node and output of the circuit must be verified for hazard-freedom to ensure correct operat… Show more

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Cited by 3 publications
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