Efficiently compiling a functional language on AMD64

Luna, Daniel; Pettersson, Mikael; Sagonas, Konstantinos

doi:10.1145/1069774.1069791

Cited by 2 publications

(2 citation statements)

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“…Luna et al [2] experimented with different register allocators on AMD64 platform. Their studies show that with more registers, a fast linear scan based register allocation algorithm [18] could produce competitive performance code with graph coloring based algorithm.…”

Section: Related Workmentioning

confidence: 99%

Performance Characterization of the 64-bit x86 Architecture from Compiler Optimizations’ Perspective

Liu

2006

Lecture Notes in Computer Science

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Abstract. Intel Extended Memory 64 Technology (EM64T) and AMD 64-bit architecture (AMD64) are emerging 64-bit x86 architectures that are fully x86 compatible. Compared with the 32-bit x86 architecture, the 64-bit x86 architectures cater some new features to applications. For instance, applications can address 64 bits of virtual memory space, perform operations on 64-bit-wide operands, get access to 16 general-purpose registers (GPRs) and 16 extended multi-media (XMM) registers, and use a register-based argument passing convention. In this paper, we investigate the performance impacts of these new features from compiler optimizations' standpoint. Our research compiler is based on the Intel Fortran/C++ production compiler, and our experiments are conducted on the SPEC2000 benchmark suite. Results show that for 64-bit-wide pointer and long data types, several SPEC2000 C benchmarks are slowed down by more than 20%, which is mainly due to the enlarged memory footprint. To evaluate the performance potential of 64-bit x86 architectures, we designed and implemented the LP32 code model such that the sizes of pointer and long are 32 bits. Our experiments demonstrate that on average the LP32 code model speeds up the SPEC2000 C benchmarks by 13.4%. For the register-based argument passing convention, our experiments show that the performance gain is less than 1% because of the aggressive function inlining optimization. Finally, we observe that using 16 GPRs and 16 XMM registers significantly outperforms the scenario when only 8 GPRs and 8 XMM registers are used. However, our results also show that using 12 GPRs and 12 XMM registers can achieve as competitive performance as employing 16 GPRs and 16 XMM registers.

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Section: Related Workmentioning

confidence: 99%

Performance Characterization of the 64-bit x86 Architecture from Compiler Optimizations’ Perspective

Liu

2006

Lecture Notes in Computer Science

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“…By now the HiPE compiler is robust, handles the complete Erlang language and produces reasonably efficient code. It comes with backends for a variety of platforms, starting with SPARC V8+ that was the first architecture it supported, continuing with x86 [15] and AMD64 (x86 64) [12], PowerPC and PowerPC64, and various flavors of the ARM family of processors.…”

Section: Introductionmentioning

confidence: 99%

ErLLVM

Sagonas

Stavrakakis

Tsiouris

2012

Proceedings of the Eleventh ACM SIGPLAN Workshop on Erlang Workshop

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This paper describes ErLLVM, a new backend for the HiPE compiler, the native code compiler of Erlang/OTP, that targets the LLVM compiler infrastructure. Besides presenting the overall architecture of ErLLVM and its integration in Erlang/OTP, we describe the changes to LLVM that ErLLVM required and discuss technical challenges and decisions we took. Finally, we provide a detailed performance evaluation of ErLLVM compared to BEAM, the existing backends of the HiPE compiler, and Erjang.

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Efficiently compiling a functional language on AMD64

Cited by 2 publications

References 12 publications

Performance Characterization of the 64-bit x86 Architecture from Compiler Optimizations’ Perspective

Performance Characterization of the 64-bit x86 Architecture from Compiler Optimizations’ Perspective

ErLLVM

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