Efficiently High Speed Implementation of AES Algorithm on FPGA

Abstract

With the increasing number of internet and wireless communication users in any organisation, data security has become a major problem for the valuable information that needs to be protected. So to protect the user data that is being transmitted over open channels some means of resilient data protection is needed. So AES can be considered as the most widely used modern symmetric key encryption standard for such sensitive data that needs to be kept secured. This paper propounds high speed implementation of AES algorithm while maintain with the minimum amount of hardware resources. The proposed AES algorithm supports 128 bit key length. In order to achieve high speed pipelined architecture is used. The AES-128 design is implemented on FPGA with XC6SLX16-3CSG324 package using Verilog language with the help of Xilinx ISE tool. Keywords: Advanced Encryption Standard (AES), Field Programmable Gate Array (FPGA). I.INTRODUCTION With the increasing need of information data in computer networks and communication technology the need of automated tools for protecting files and other information is growing. This data is handled by public networks and is vulnerable. So for such sensitive data that needs to be kept safe and protected from automated spying or hacking, cryptography becomes important. AES is used as the most widely used symmetric cryptographic algorithm to keep the data confidentiality [1]. In 2001, NIST announced the rijandael algorithm from Belgium has been selected as the Advanced Encryption Standard (AES) algorithm after replacing the Data Encryption Standard (DES) [2]. DES was the block cipher that was the first encryption algorithm recommended by the NIST in 1974 [3]. AES can be implemented both in hardware and software. The software implementation of AES is a slow process and thus consumes lots of processing time and also requires regular updates. Moreover the software implementation results in higher costs. While on the other hand the hardware implementation is fast, reliable and is also suitable for high speed applications, without the need of any system update. Moreover hardware implementation does not require any system resources as used in software implementation of AES. Hardware implementation of AES proves to be physically secured as compared to software implementation as the outside attackers cannot modify them. so due to these reasons hardware implementation is widely used for real time applications. Normally there are two platforms for hardware implementations of AES: (1) Application Specific Integrated Circuits (ASICs) (2) Field Programmable Gate Array (FPGA). Among them FPGA as a platform is more efficient as in FPGA implementation can be updated in order to introduce a new feature partially or during run time. Moreover the currently used FPGAs have several features like block memory (BRAM), Digital Signal Processing (DSP) cores and embedded CPUs [8]. The rest of the paper is organized as follows. Section II presents a brief overview of AES and section III provides the proposed work. S...

FPGA implementation of AES algorithm for high speed applications

“…So it can be implemented using Composite Field Arithmetic (CFA) which will decrease the computation cost [12]. AES algorithm throughput can be increased by using folded parallel architecture [13].Through put can be further increased by introducing 2-slow retiming technique [14].A light weight Mix Column structure can be designed using [16]. By using X time based MixColumn transformation the speed circuit can be increased along the reduced area [17][18][19][20][21][22][23][24][25].…”