Electrical and structural properties of polycrystalline silicon

Tringe, Joseph W.; Plummer, J.D.

doi:10.1063/1.373475

Cited by 40 publications

(23 citation statements)

References 15 publications

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“…It has also been reported that individual GBs have different structural and electrical properties. 5,6 Thus control of the electrical properties of GBs is vital for nanometerscale devices, in which only a few grains and GBs may exist in the active region.In this letter we discuss the effect of oxidation and thermal annealing on the electrical and structural properties of poly-Si thin films and on nanowires fabricated in these films. We observe that the film electrical conductivity ͑ ͒ decreases nonmonotonically with an increase in oxidation temperature and that a two-stage oxidation process, followed by annealing, reduces variation in the activation energy of the conductivity (E a ) and tunnel resistance (R T ) in nanowire devices.…”

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Control of grain-boundary tunneling barriers in polycrystalline silicon

Kamiya

Durrani

Ahmed

2002

Applied Physics Letters

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The effect of oxidation and annealing on the electrical properties of grain boundaries ͑GBs͒ in heavily doped polycrystalline silicon is characterized using bulk films and 30-nm-wide nanowires. Oxidation at 650-750°C selectively oxidizes the GBs. Subsequent annealing at 1000°C increases the associated potential barrier height and resistance. These observations can be explained by structural changes in the Si-O network at the GBs and the competition between surface oxygen diffusion and oxidation from the GBs in the crystalline grains. A combination of oxidation and annealing may provide a method that can better control the GB potential barriers. © 2002 American Institute of Physics. ͓DOI: 10.1063/1.1509853͔The structural and electrical properties of polycrystalline silicon ͑poly-Si͒ thin films are of great interest in the design of ultralarge-scale integrated ͑ULSI͒ circuits and thin-film transistors for flat panel displays. 1,2 As ULSI design rules are reduced to the nanometer scale, the poly-Si microstructure can strongly influence the device characteristics. If poly-Si grains are a few tens of nanometer in size, the material is of considerable interest for the fabrication of nanometer-scale devices such as single-electron transistors. 3,4 Variation between individual grains and grain boundaries ͑GBs͒ causes nonuniformity in the electrical characteristics of different devices. It has also been reported that individual GBs have different structural and electrical properties. 5,6 Thus control of the electrical properties of GBs is vital for nanometerscale devices, in which only a few grains and GBs may exist in the active region.In this letter we discuss the effect of oxidation and thermal annealing on the electrical and structural properties of poly-Si thin films and on nanowires fabricated in these films. We observe that the film electrical conductivity ͑ ͒ decreases nonmonotonically with an increase in oxidation temperature and that a two-stage oxidation process, followed by annealing, reduces variation in the activation energy of the conductivity (E a ) and tunnel resistance (R T ) in nanowire devices. We propose that oxygen atoms are incorporated selectively into the GBs and that this effect determines the electrical characteristics.Our poly-Si film was prepared by solid-phase crystallization of 50-nm-thick amorphous silicon at 850°C for 30 min. 6 The films were doped n type to 10 20 /cm 3 using phosphorus ion implantation. Transmission electron microscopy ͑TEM͒ indicated that the grains were columnar with lateral size of 20-150 nm and that the GBs were no thicker than 1 nm. 7 The bulk film was characterized electrically using a large-area ͑100 m contact spacing͒ transmission-line mode ͑TLM͒ test structure. Nanowire structures ͑30 nm wide and 20 nm-80 nm long͒ were used to investigate the microscopic properties over a few GBs. The nanowires were defined by electron-beam lithography in polymethyl methacrylate resist, followed by reactive-ion etching ͑RIE͒ in a 1:1 plasma of SiCl 4 and CF 4 . 6 Ohmic contacts ...

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confidence: 99%

Control of grain-boundary tunneling barriers in polycrystalline silicon

Kamiya

Durrani

Ahmed

2002

Applied Physics Letters

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“…GB's observed in poly-Si are roughly classified into a twin boundary and a random GB. Experimental results showed that twin boundaries were electrically inactive, 4) and it is thought that twin boundaries do not affect the electrical property of poly-Si. In contrast, random GB's are thought to deteriorate the electrical and mechanical properties of poly-Si, since dangling-bonds are possibly formed at these boundaries.…”

Section: Introductionmentioning

confidence: 99%

Molecular Dynamics Simulation of Grain Boundary Formation and Migration in Silicon

2006

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Molecular dynamics simulation using Tersoff potential was carried out to investigate the formation and the migration of (010) AE5 twist boundary in silicon. Effects of carbon atoms on the grain boundary formation and the grain boundary migration were also investigated. Amorphous thin layers remained at the twist boundary even after crystallization, and changes in the thickness of this layers caused grain boundary migration. When carbon atoms were segregated at the twist boundary, these atoms prevented shrinkage of an amorphous thin layer, and the grain boundary migration was retarded. Precipitated carbon atoms within the grain produces a strain field and this strain field possibly became driving force for the grain boundary migration.

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“…In addition, the transport properties of these heterogeneous materials are affected significantly by local microstructures. Thus carrier transport has been investigated in localized regions using an AFM/STM [4] and by fabricating wires ranging 0.1 µm -4 µm in width [5]. In this paper, we report the fabrication of very thin nc-Si:H films and their characterization using 30-nm-wide nanowires to investigate the local carrier transport properties.…”

Section: Introductionmentioning

confidence: 99%

Carrier Transport in Ultra-Thin Nano/Polycrystalline Silicon Films and Nanowires

Kamiya¹,

Tan²,

Furuta³

et al. 2001

MRS Proc.

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Carrier transport was investigated in two different types of ultra-thin silicon films, polycrystalline silicon (poly-Si) films with large grains > 20 nm in size and hydrogenated nanocrystalline silicon (nc-Si:H) films with grains 4 nm -8 nm in size. It was found that there were local non-uniformities in grain boundary potential barriers in both types of films.Single-electron charging effects were observed in 30 nm × 30 nm nanowires fabricated in 30 nm-thick nc-Si:H films, where the electrons were confined in crystalline silicon grains encapsulated by amorphous silicon. In contrast, the poly-Si nanowires of similar dimensions showed thermionic emission over the grain boundary potential barriers formed by carrier trapping in grain boundary defects.

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Electrical and structural properties of polycrystalline silicon

Cited by 40 publications

References 15 publications

Control of grain-boundary tunneling barriers in polycrystalline silicon

Control of grain-boundary tunneling barriers in polycrystalline silicon

Molecular Dynamics Simulation of Grain Boundary Formation and Migration in Silicon

Carrier Transport in Ultra-Thin Nano/Polycrystalline Silicon Films and Nanowires

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