Electrical and structural properties of solid phase crystallized polycrystalline silicon and their correlation to single-electron effects

Microcrystalline silicon ( c-Si:H) thin films were prepared at 300°C on glass. Their structure and transport properties were studied in a wide range of film thickness ranging from 10 nm to 1 m. The crystal fraction increases monotonously from ϳ64% to ϳ100% as film thickness increases. Electron mobility first increases with increasing film thickness at thicknesses smaller than 50 nm but saturates at larger thickness. This mobility behavior is explained by percolation transport through crystalline grains. These results are different from those obtained with preferentially oriented polycrystalline silicon films. It is related to the difference in the microstructure evolution in which subsequent film growth is influenced by the growth surface structure. A single-electron transistor fabricated in 30-nm-thick c-Si:H exhibits Coulomb blockade effects at 4.2 K. This result indicates that amorphous phases which exist between crystalline grains behave as tunnel barrier for electrons.

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“…29 for details͒. The nanowire was 1 m long and 60 nm wide and the side gates to the nanowire separation were 120 nm ͑Fig.…”

Section: B Fabrication Of Setsmentioning

confidence: 99%

Growth, structure, and transport properties of thin (>10 nm) n-type microcrystalline silicon prepared on silicon oxide and its application to single-electron transistor

Kamiya

Nakahata

Tan

et al. 2001

Journal of Applied Physics

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“…Transmission electron microscopy ͑TEM͒ indicated that the grains were columnar with lateral size of 20-150 nm and that the GBs were no thicker than 1 nm. 7 The bulk film was characterized electrically using a large-area ͑100 m contact spacing͒ transmission-line mode ͑TLM͒ test structure. Nanowire structures ͑30 nm wide and 20 nm-80 nm long͒ were used to investigate the microscopic properties over a few GBs.…”

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confidence: 99%

“…It is known that impurity diffusion in GBs is greater than in crystalline grains. 7,9,10 We therefore attribute the third region to oxygen diffusion in the GBs. Table I shows the silicon thickness consumed by the surface oxide (d s ) and the GB oxygen diffusion length (l GB ).…”

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confidence: 99%

Control of grain-boundary tunneling barriers in polycrystalline silicon

Kamiya

Durrani

Ahmed

2002

Applied Physics Letters

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The effect of oxidation and annealing on the electrical properties of grain boundaries ͑GBs͒ in heavily doped polycrystalline silicon is characterized using bulk films and 30-nm-wide nanowires. Oxidation at 650-750°C selectively oxidizes the GBs. Subsequent annealing at 1000°C increases the associated potential barrier height and resistance. These observations can be explained by structural changes in the Si-O network at the GBs and the competition between surface oxygen diffusion and oxidation from the GBs in the crystalline grains. A combination of oxidation and annealing may provide a method that can better control the GB potential barriers. © 2002 American Institute of Physics. ͓DOI: 10.1063/1.1509853͔The structural and electrical properties of polycrystalline silicon ͑poly-Si͒ thin films are of great interest in the design of ultralarge-scale integrated ͑ULSI͒ circuits and thin-film transistors for flat panel displays. 1,2 As ULSI design rules are reduced to the nanometer scale, the poly-Si microstructure can strongly influence the device characteristics. If poly-Si grains are a few tens of nanometer in size, the material is of considerable interest for the fabrication of nanometer-scale devices such as single-electron transistors. 3,4 Variation between individual grains and grain boundaries ͑GBs͒ causes nonuniformity in the electrical characteristics of different devices. It has also been reported that individual GBs have different structural and electrical properties. 5,6 Thus control of the electrical properties of GBs is vital for nanometerscale devices, in which only a few grains and GBs may exist in the active region.In this letter we discuss the effect of oxidation and thermal annealing on the electrical and structural properties of poly-Si thin films and on nanowires fabricated in these films. We observe that the film electrical conductivity ͑ ͒ decreases nonmonotonically with an increase in oxidation temperature and that a two-stage oxidation process, followed by annealing, reduces variation in the activation energy of the conductivity (E a ) and tunnel resistance (R T ) in nanowire devices. We propose that oxygen atoms are incorporated selectively into the GBs and that this effect determines the electrical characteristics.Our poly-Si film was prepared by solid-phase crystallization of 50-nm-thick amorphous silicon at 850°C for 30 min. 6 The films were doped n type to 10 20 /cm 3 using phosphorus ion implantation. Transmission electron microscopy ͑TEM͒ indicated that the grains were columnar with lateral size of 20-150 nm and that the GBs were no thicker than 1 nm. 7 The bulk film was characterized electrically using a large-area ͑100 m contact spacing͒ transmission-line mode ͑TLM͒ test structure. Nanowire structures ͑30 nm wide and 20 nm-80 nm long͒ were used to investigate the microscopic properties over a few GBs. The nanowires were defined by electron-beam lithography in polymethyl methacrylate resist, followed by reactive-ion etching ͑RIE͒ in a 1:1 plasma of SiCl 4 and CF 4 . 6 Ohmic contacts ...

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“…We have reported previously the film microstructure for the poly-Si film [7]. The Raman spectra showed a sharp peak corresponding to crystalline silicon grains at ~ 520 cm -1 and a broad peak at A16.2.2 ~500 cm -1 .…”

Section: Results and Discussion Film Structurementioning

confidence: 83%

Carrier Transport in Ultra-Thin Nano/Polycrystalline Silicon Films and Nanowires

Kamiya¹,

Tan²,

Furuta³

et al. 2001

MRS Proc.

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Carrier transport was investigated in two different types of ultra-thin silicon films, polycrystalline silicon (poly-Si) films with large grains > 20 nm in size and hydrogenated nanocrystalline silicon (nc-Si:H) films with grains 4 nm -8 nm in size. It was found that there were local non-uniformities in grain boundary potential barriers in both types of films.Single-electron charging effects were observed in 30 nm × 30 nm nanowires fabricated in 30 nm-thick nc-Si:H films, where the electrons were confined in crystalline silicon grains encapsulated by amorphous silicon. In contrast, the poly-Si nanowires of similar dimensions showed thermionic emission over the grain boundary potential barriers formed by carrier trapping in grain boundary defects.

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Electrical and structural properties of solid phase crystallized polycrystalline silicon and their correlation to single-electron effects

Cited by 20 publications

References 23 publications

Growth, structure, and transport properties of thin (>10 nm) n-type microcrystalline silicon prepared on silicon oxide and its application to single-electron transistor

Growth, structure, and transport properties of thin (>10 nm) n-type microcrystalline silicon prepared on silicon oxide and its application to single-electron transistor

Control of grain-boundary tunneling barriers in polycrystalline silicon

Carrier Transport in Ultra-Thin Nano/Polycrystalline Silicon Films and Nanowires

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Electrical and structural properties of solid phase crystallized polycrystalline silicon and their correlation to single-electron effects

Cited by 20 publications

References 23 publications

Growth, structure, and transport properties of thin (&gt;10 nm) n-type microcrystalline silicon prepared on silicon oxide and its application to single-electron transistor

Growth, structure, and transport properties of thin (&gt;10 nm) n-type microcrystalline silicon prepared on silicon oxide and its application to single-electron transistor

Control of grain-boundary tunneling barriers in polycrystalline silicon

Carrier Transport in Ultra-Thin Nano/Polycrystalline Silicon Films and Nanowires

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Growth, structure, and transport properties of thin (>10 nm) n-type microcrystalline silicon prepared on silicon oxide and its application to single-electron transistor

Growth, structure, and transport properties of thin (>10 nm) n-type microcrystalline silicon prepared on silicon oxide and its application to single-electron transistor