Electrical assessment of copper damascene interconnects down to sub-50 nm feature sizes

Steinlesberger, G.; Engelhardt, M.; Schindler, G.; Steinhögl, W.; Glasow, A. von; Mosig, K.; Bertagnolli, E.

doi:10.1016/s0167-9317(02)00815-8

Cited by 80 publications

(43 citation statements)

References 4 publications

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“…Therefore, the development of Cu filling process without voids is mandatory for producing very narrow Cu wiring with low resistivity and high reliability. [5][6][7][8] The dual damascene process is widely used for Cu wiring. In this process, Cu wiring is fabricated by repeatedly filling Cu in narrow trenches followed by chemical mechanical polishing (CMP).…”

Section: Introductionmentioning

confidence: 99%

Influence of Minimum Barrier Metal Thickness at Trenches on Void Formation in 50-nm-wide Cu Wiring

Chonan

Aoyama

Khoo³

et al. 2014

Electrochemistry

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In order to completely fill the 50 nm wide high aspect ratio trenches with Cu electroplating, we investigated the influence of barrier metal thicknesses on the voids formation in the trenches. The void occurrence rates were decreased significantly with increasing minimum barrier metal thickness at the side wall of trenches, and it becomes less than 1% when the minimum thickness becomes thicker than 4.6 nm independent of width and aspect ratio of trenches. Resistivities of Cu wires with minimum total barrier metal thickness thicker than 4.6 nm by electroplating, annealing at 573 K for 30 min were found to be almost the same level as those listed in ITRS.

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Section: Introductionmentioning

confidence: 99%

Influence of Minimum Barrier Metal Thickness at Trenches on Void Formation in 50-nm-wide Cu Wiring

Chonan

Aoyama

Khoo³

et al. 2014

Electrochemistry

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“…1) However, there is a significant increase in resistivity in copper interconnects when line widths are less than 100 nm. [1][2][3][4][5][6][7] This is becoming a critical issue and is mainly due to the fact that the line widths are comparable to the mean free path of an electron (39 nm), which causes an increase in resistivity by electron scattering occurring at the grain boundaries of the Cu interconnects. Therefore, it is necessary to develop a grain coarsening process to achieve low resistivity in very narrow Cu interconnects.…”

Section: Introductionmentioning

confidence: 99%

Microstructures of 50-nm Cu Interconnects along the Longitudinal Direction

et al. 2007

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Grain size distributions and average grain sizes in the longitudinal direction of the Cu interconnect in 50-, 70-and 80-nm-wide Cu interconnects were evaluated and compared with the resistivities of each interconnect. After annealing, the standard deviation of grain sizes for 50-nm Cu interconnect increased to 27.5, and the average grain size microstructure grew to larger than that of as-deposited 50-nm Cu interconnects. The value of standard deviation of grain sizes in the normal distribution histogram for a 50-nm wire was found to be much smaller than those for 70-and 80-nm Cu wires after annealing. This implies that adequate grain growth should not be expected in the very narrow Cu interconnects (less than 50-nm) of the future if they are made with the conventional annealing process.

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“…Although these phenomena have their foundations at the atomic and grain scales, their impact can be observed in manufactured systems, such as in the performance and reliability of metal interconnects in integrated circuits (ICs), [14][15][16][17] for example, grain size distributions in Cu interconnects have a direct relation to electrical resistivity (see for example Steinlesberger et al 3,18 ). Void formation in interconnect structures is also impacted by grain structure, whether caused by electromigration, 8,9 or by stress-induced migration.…”

Section: Introductionmentioning

confidence: 99%

Stress-Induced Grain Boundary Migration in Polycrystalline Copper

Bloomfield

Bentz

Cale

2007

Journal of Elec Materi

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We use three-dimensional (3D) grain-continuum models to study grain boundary migration, treating each grain with anisotropic elastic properties. Grain boundary speeds are computed using a finite element method to calculate differences in strain energy density across grain boundaries. Bodyfitted finite element meshes are used. An interface tracking program, PLENTE, is used to develop starting structures and move the grain boundaries based on these speeds. We demonstrate this procedure on textured films consisting of h100i and h111i fiber textured film. We also apply the model to a short section of a Cu line embedded in oxide. We conclude with a discussion on the relative impact of different driving forces for grain boundary motion.

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Electrical assessment of copper damascene interconnects down to sub-50 nm feature sizes

Cited by 80 publications

References 4 publications

Influence of Minimum Barrier Metal Thickness at Trenches on Void Formation in 50-nm-wide Cu Wiring

Influence of Minimum Barrier Metal Thickness at Trenches on Void Formation in 50-nm-wide Cu Wiring

Microstructures of 50-nm Cu Interconnects along the Longitudinal Direction

Stress-Induced Grain Boundary Migration in Polycrystalline Copper

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