Electrical characteristics of contacts to thin film N-polar n-type GaN

Kim, Hyunsoo; Ryou, Jae Hyun; Dupuis, R. D.; Lee, Sung Nam; Park, Yongjo; Jeon, Joon Woo; Seong, Tae Yeon

doi:10.1063/1.3013838

Cited by 71 publications

(52 citation statements)

References 15 publications

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“…Ti/Al/Ni/Au is deposited as an ohmic contact without annealing. [ 27 ] All the FETs have been treated with O 2 plasma to reduce surface state effects. [ 28 ] Due to the thick dielectric layer (250 nm), the FET has relatively high gate voltage.…”

Section: Field Effect Transistormentioning

confidence: 99%

Single Crystal Gallium Nitride Nanomembrane Photoconductor and Field Effect Transistor

Xiong

Park

Song

et al. 2014

Adv Funct Materials

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We report in this work the fabrication of single crystal GaN nanomembranes, with a thickness as low as 50 nm. Large area (≥5 mm × 5 mm) GaN membranes are produced by electrochemical etching (ECE) with a special high-conductivity sacrifi cial underlayer. Large-area, crackfree transfer of GaN NMs have been performed onto metal, glass, and polymer target substrates. The transport properties of freestanding GaN nanomembranes are analyzed using UV-assisted Hall measurements. The interaction of the carriers with the surface electronic states are investigated by the intensity dependence of the photoconductor gain, and by the temperature-dependent measurements of photocurrent decay. The transport property of GaN NM, down to a thickness of 90 nm, remains very comparable to that from much thicker GaN structures. Enhancement-mode fi eld effect transistors (FETs) have been fabricated and demonstrated on a SiO 2 / Si(001) wafer, suggesting that GaN nanomembranes can be a new candidate for fl exible electronics requiring high power and high-frequency. Results and Discussion Nanomembrane FabricationThe principle of using an ECE process to selectively remove underlying GaN sacrifi cial layers has been described before. [ 12,13 ] Multi-layered GaN structures having nanomembrane layers (50 to 500 nm thick) on top of heavily-doped ( n ≈ 1 × 10 19 cm −3 ) GaN sacrifi cial layers were grown by metal-organic chemical vapor deposition (MOCVD) process on sapphire. To obtain large-area NM within a reasonable time, a periodic array of via holes were created such that the undercut etching can proceeds uniformly around these openings. The via-holes are squares with a dimension of 10 µm and a diagonal periodicity of 25, 50, and 100 µm. These holes were created by Cl-based inductively coupled plasma (ICP) etching to expose the sacrifi cial layer. The photoresist (Shipley S1827) used during the Cl-ICP etching was retained to protect the front surface of the membrane during ECE. The nanomembrane layers became detached from the substrate once the undercut regions around each opening coalesce with the adjacent ones. GaN NMs were cleaned by rinsing sequentially in DI water, acetone and isopropyl-alcohol (IPA). After cleaning, they were transferred on to other substrates Single Crystal Gallium Nitride Nanomembrane Photoconductor and Field Effect Transistor Kanglin Xiong , Sung Hyun Park , Jie Song , Ge Yuan , Danti Chen , Benjamin Leung , and Jung Han * Large-area, free-standing and single-crystalline GaN nanomembranes are prepared by electrochemical etching from epitaxial layers. As-prepared nanomembranes are highly resistive but can become electronically active upon optical excitation, with an excellent electron mobility. The interaction of excited carriers with surface states is investigated by intensity-dependent photoconductivity gain and temperature-dependent photocurrent decay. Normally off enhancement-type GaN nanomembrane MOS transistors are demonstrated, suggesting that GaN could be used in fl exible electronics for high power and hig...

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Section: Field Effect Transistormentioning

confidence: 99%

Single Crystal Gallium Nitride Nanomembrane Photoconductor and Field Effect Transistor

Xiong

Park

Song

et al. 2014

Adv Funct Materials

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“…Here, note that the n value, which was calculated using the relation of n=(E00/kT)coth(E00/kT), was much larger than 1.0 for all cases, indicating that non-ideal carrier transport occurred at the ITO contact interface. According to previous studies, [15,16] carrier transport through surface states associated with point defects such as nitrogen vacancies or oxygen interstitials (generated during ITO sputtering) or threading dislocations might be responsible for the nonideal transport at the contact interface. Notably, however, the n value decreased significantly with post-thermal annealing, indicating that the density of surface states were reduced.…”

Section: Resultsmentioning

confidence: 99%

Excellent Schottky Characteristics of Indium-tin-oxide Contact to n-type GaN

Kim¹,

Gil²,

Kim³

2015

Proceedings of the 2nd International Conference on Civil, Materials and Environmental Sciences

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Abstract-Excellent Schottky characteristics of indium-tinoxide (ITO) contact formed on n-type GaN (n-GaN) were demonstrated. The post-thermal annealing of ITO contact sputtered on n-GaN led to a significant improvement in the Schottky characteristics, particularly pronounced in the air ambient than nitrogen ambient, e.g., the rectification ratio (measured at ± 1.0 V) was increased from 4.9 to 4240 after an optimized post-thermal annealing. Thermionic field emission model applied to the forward current-voltage curves of the ITO/n-GaN Schottky diodes also exhibited that the Schottky barrier height could be as high as 0.93 eV. The observed excellent Schottky characteristics with postthermal annealing are attributed to the improved ITO crystallinity as verified by glancing X-ray diffraction method

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“…One of the ways of maximizing the EQE is to increase current injection by forming low resistance ohmic contacts and thereby to increase radiative recombination efficiency [9][10][11][12][13]. For c-plane n-GaN, Ti/Al-based metal contacts have been widely investigated because Ti/Al-based schemes easily formed low-resistance ohmic contact when annealed above 600 °C [14][15][16].…”

Section: Introductionmentioning

confidence: 99%

“…[1] It is well known that these polar LEDs suffer from the quantum-confined Stark effect (QCSE) [2] induced by large polarization-induced internal electric fields, resulting in a separation between the electron and hole wave functions in the quantum wells (QWs) and so reducing radiative recombination efficiency. [3][4][5] Thus, to enhance the internal quantum efficiency by eliminating or minimizing the Stark effect, GaN-based LEDs were grown on non-polar or semipolar substrates, e.g., (11)(12)(13)(14)(15)(16)(17)(18)(19)(20), and (11)(12)(13)(14)(15)(16)(17)(18)(19)(20)(21)(22) plane substrates [5][6][7][8]. For example, Chakraborty et al [6], investigating the DC and pulsed performance of InGaN/GaN multipleQWs LEDs grown on non-polar free-standing m-plane GaN substrates, showed that packaged LEDs (300 × 300 µm 2 ) (a wavelength of 452 nm) yielded a CW output power as high as 0.6 mW at a current of 20 mA, corresponding to an external quantum efficiency of 1.09%.…”

Section: Introductionmentioning

confidence: 99%