Electrical characteristics of gate-all-around MOSFET ring oscillators using TCAD simulation

Kim, Sutae; Kim, Minsuk; Woo, Sola; Kang, Hyungu; Kim, Sangsig

doi:10.1109/vlsi-tsa.2018.8403835

Cited by 3 publications

(3 citation statements)

References 2 publications

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“…Based on the analysis of the impact of SHE, figure 8(b) shows the T L -vs-|V GS | and I DS -vs-|V GS | in n-/p-type JL-NC CFET. The lattice temperature in figure 8(b) was calculated as the average value of the temperatures of SiO 2 and HZO to avoid overestimating the SHE [19]. As I DS -vs-|V GS | with and without SHE are almost identical (see figure 8(b)), we can predict that the results of the proposed device design guidelines would not significantly differ from those with considering SHE.…”

Section: She In Jl-nc Cfetmentioning

confidence: 98%

“…SHE must be considered to evaluate whether the performance improvement from using the NC device structure is accurately predicted or not. JL-NC CFETs were simulated with thermodynamic models that enable the analysis of SHE in [19]. The low lattice temperature of JL-NC CFETs is due to the nanosheet device structure and junctionless doping profile in the channel [29,30].…”

Section: She In Jl-nc Cfetmentioning

confidence: 99%

“…Using the ferroelectric HZO layer in JL-CFET, we can find the sweet spot of JL-CFET device design, to meet the WF margin as well as to implement a higher on-state drive current. In addition, since it is crucial to understand the selfheating effect (SHE) [18,19] for the purpose of accurately predicting the performance gains from using the NC characteristics, we analyze the impact of SHE on device performance.…”

Section: Introductionmentioning

confidence: 99%

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Design of JL-CFET (junctionless complementary field effect transistor)-based inverter for low power applications

Lee¹,

Choi²,

Son³

et al. 2022

Semicond. Sci. Technol.

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Junctionless complementary field effect transistor (JL-CFET) is an emerging device that needs a small layout area and low fabrication cost. However, in order for the JL-CFET to be adopted for low power applications, two main constraints need to be overcome: (1) a high work function of metal gate and (2) a low drain current. In this work, an optimal device design is proposed to overcome those problems, by analyzing various performance metrics, such as on-state drive current, subthreshold swing, drain induced barrier lowering, propagation delay time, and ring oscillator’s oscillation frequency, which are extracted from various structures of JL-CFET. In addition, the negative capacitance effect in JL-CFET is examined to address the limit from device structures.

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Section: She In Jl-nc Cfetmentioning

confidence: 98%