Electrical Characterization of Germanium Oxide/Germanium Interface Prepared by Electron-Cyclotron-Resonance Plasma Irradiation

Fukuda, Yukio; Ueno, Tomoo; Hirono, Shigeru; Hashimoto, Satoshi

doi:10.1143/jjap.44.6981

Cited by 87 publications

(56 citation statements)

References 13 publications

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“…Yet, recent reports show good passivation using germanium oxide both on n-and p-type Ge. Applying GeO 2 prepared by electron-cyclotron-resonance plasma irradiation resulted in an interface trap density (D it ) of ~6 × 10 10 cm -2 eV -1 at the midgap, measured by the ac conductance method ( 8 ). Thermal oxidation and photo-oxidation of Ge were also investigated (8, 9 , 10 , 11 ).…”

Section: Introductionmentioning

confidence: 99%

Atomic Layer Deposition of High-k Dielectric Layers on Ge and III-V MOS Channels

Delabie¹,

Alian²,

Bellenger³

et al. 2008

ECS Trans.

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Document VersionPublisher's PDF, also known as Version of Record (includes final page, issue and volume numbers)Please check the document version of this publication:• A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website.• The final author version and the galley proof are versions of the publication after peer review.• The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication Citation for published version (APA):Delabie, A., Alian, A., Bellenger, F., Brammertz, G., Brunco, D. P., Caymax, M., ... . Atomic layer deposition of high-k dielectric layers on Ge and III-V MOS channels. ECS Transactions, 16(10), 671-685. DOI: 10.1149/1.2986824 General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal ? Take down policyIf you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim.

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Section: Introductionmentioning

confidence: 99%

Atomic Layer Deposition of High-k Dielectric Layers on Ge and III-V MOS Channels

Delabie¹,

Alian²,

Bellenger³

et al. 2008

ECS Trans.

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“…The thickness of GeO 2 and Al 2 O 3 was 20 nm and 20 nm, respectively. The source/drain regions were formed in a self-align way by boron ion implantation under the condition of a dose of 1x10 15 cm -2 at 10 keV. The activation annealing was carried out at 450 °C in N 2 gas.…”

Section: Ge Gate Stack Technologiesmentioning

confidence: 99%

(Invited) MOS Interface Control Technologies for III-V/Ge Channel MOSFETs

et al. 2011

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MOSFETs using channel materials with low effective mass have been regarded as strongly important for obtaining high current drive and low supply voltage CMOS under sub 10 nm regime. From this viewpoint, attentions have recently been paid to III-V and Ge channels. However, one of the most critical issues for realizing Ge/III-V MOSFETs is gate insulator formation with superior MOS interface quality on Ge/III-V. In this paper, we focus on the possible solutions for gate stack technologies on Ge/III-V. As for Ge, GeO 2 /Ge interfaces have been regarded as promising. However, these interfaces have still employed thick GeO 2 layers. Recently, we have succeeded in thin EOT gate stacks with Ge oxide interfacial layers by using ECR plasma post oxidation. The high quality Al 2 O 3 /GeO x /Ge gate stacks were fabricated by exposing the ALD Al 2 O 3 /Ge structures to ECR oxygen plasma and oxidizing the Ge surface through the very thin ALD Al 2 O 3 layer. We present our recent results of the interface properties using this interface. As for InGaAs channels, we have also proposed a novel interfacial control technology utilizing InGaAs surface nitridation by ECR nitrogen plasma and successive post metallization annealing. This interfacial layer combined with an ECR sputtering SiO 2 or an ALD Al 2 O 3 gate insulator is shown to reduce D it down to low order of 10 11 cm -2 eV -1 . The physical origin of this D it reduction and the role of the nitridation are discussed.

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“…Ge pMOSFET with metal source/drain has a further potential as future high performance CMOS devices. Another promising interfacial layer is a GeO 2 /Ge interface, which has been reported to provide the superior interface properties [20][21][22][23][24][25][26][27][28]. We have shown that GeO 2 /Ge interfaces with a quite low interface state density can be realized by direct thermal oxidation of Ge substrates [27,28].…”

Section: (110)mentioning

confidence: 99%

High mobility channel CMOS technologies for realizing high performance LSI's

Takagi

2009

2009 IEEE Custom Integrated Circuits Conference

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Saturation of CMOS performance has been evident in the present 45/32 nm technology node, because of a variety of physical limitations on the miniaturization. Thus, channel engineering, including the enhancement of drive current due to high mobility channel materials and with robustness against short channel effects and characteristic variation due to multi-gate structures, has currently been recognized as mandatory for high performance CMOS. In this paper, we report our approaches to further improvement of MOSFETs by using strained-Si, SiGe, Ge and III-V semiconductor channels on the Si CMOS platform with an emphasis on the combination of ultra-thin body and multi-gate structures. IntroductionThe device scaling concept, which can lead to the increase in both the switching speed and the number density of MOSFETs under reasonable power consumption, had been the main guiding principle of the MOS device engineering over these thirty years. It has been recognized, however, below 32 nm technology node that this conventional device scaling has confronted the difficulty that the three main indices associated with MOSFET performance, on-current, power consumption and short channel effects, have the trade-off relationship with each other, owing to several physical and essential limitations directly related to the device miniaturization, such as tunneling current, mobility reduction, source/drain resistance, inversion-layer capacitance and Sub-threshold slope.Fig. 1 Schematic log I ds -V g characteristics to show the factor affecting power consumption.Fig. 1 shows a schematic Id-Vg curve of MOSFETs.Here, the power consumption, P consum , and the on current, I on , can be roughly described [1] bywhere a, f, C load , I 0 , S, I leak , N s , C g and υ are a constant value, the operating frequency, the load capacitance, the drain current at V g of V th , the Sub-threshold slope, the total leakage current including gate and junction leakages, the induced surface carrier concentration in the channel, the gate capacitance and the velocity near the source region, respectively. In order to realize low power MOSFETs, lower V dd , higher V th , smaller S (higher immunity to short channel effects) and lower I leak are necessary. However, these requirements clearly conflict with high I on , which is still important for signal processing. Also, these requirements pose severe trade-off relationship on choosing device parameters like gate oxides thickness, T ox , substrate impurity concentration, N sub , meaning that it is physically difficult to further improve the performance and power consumption under the conventional Si CMOS scheme. Source Engineering Gate Stack Engineering metal gate high k Channel Engineering SOI Strained Si, Ge, III-V Back gate, Fin Structure, Double gate, Nano-wire etc. Mobility, velocity, ballistic transport Carrier injection velocity Ultra-shallow junction, source resistance, metal S/D Suppression of SCE EOT Inversion-layer thickness Steep impurity profileFig. 2 Schematic diagram of three types of device enginee...

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Electrical Characterization of Germanium Oxide/Germanium Interface Prepared by Electron-Cyclotron-Resonance Plasma Irradiation

Cited by 87 publications

References 13 publications

Atomic Layer Deposition of High-k Dielectric Layers on Ge and III-V MOS Channels

Atomic Layer Deposition of High-k Dielectric Layers on Ge and III-V MOS Channels

(Invited) MOS Interface Control Technologies for III-V/Ge Channel MOSFETs

High mobility channel CMOS technologies for realizing high performance LSI's

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