Electrical characterization of si nanowire GAA-TFET based on dimensions downscaling

Abdul-kadir, Firas Natheer; Hashim, Yasir; Shakib, Muhammad Nazmus; Taha, Faris Hassan

doi:10.11591/ijece.v11i1.pp780-787

Cited by 5 publications

(3 citation statements)

References 23 publications

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“…Gate1 and Gate2 are implanted by (ϕ =3.9 eV), Gate3, and Gate4 (ϕ =4.0 eV). The structure of the device is making the concentrations distribution electron and hole are available regular at source and drain electrode, which make better control and a great ON current-state [28]- [30]. The concentration of substrate region (body) is 1×10 15 cm -3 which represents the silicon intrinsic and the length of the channel is 43 nm.…”

Section: Device Structure and Parametersmentioning

confidence: 99%

Characterization of silicon tunnel field effect transistor based on charge plasma

Abdul-kadir

Taha

2022

IJEECS

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The aim of the proposed paper is an analytical model and realization of the characteristics for tunnel field-effect transistor (TFET) based on charge plasma (CP). One of the most applications of the TFET device which operates based on CP technique is the biosensor. CP-TFET is to be used as an effective device to detect the uncharged molecules of the bio-sample solution. Charge plasma is one of some techniques that recently invited to induce charge carriers inside the devices. In this proposed paper we use a high work function in the source (ϕ=5.93 eV) to induce hole charges and we use a lower work function in drain (ϕ=3.90 eV) to induce electron charges. Many electrical characterizations in this paper are considered to study the performance of this device like a current drain (ID) versus voltage gate (Vgs), ION/IOFF ratio, threshold voltage (VT) transconductance (gm), and sub-threshold swing (SS). The signification of this paper comes into view enhancement the performance of the device. Results show that high dielectric (K=12), oxide thickness (Tox=1 nm), channel length (Lch=42 nm), and higher work function for the gate (ϕ=4.5 eV) tend to best charge plasma silicon tunnel field-effect transistor characterization.

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Section: Device Structure and Parametersmentioning

confidence: 99%

Characterization of silicon tunnel field effect transistor based on charge plasma

Abdul-kadir

Taha

2022

IJEECS

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“…The Nano-dimensional electronic devices such as diodes, transistors, capacitors, and resistors, have newly become marketable in the industry of electronics because of their so tiny applicable circuits. The characteristics of these Nano devices, which may correspond to enormous novel applications [16]- [20], will likely build on the Nano-dimensional feature of such devices. The new versions of chips with these comparatively novel and Nano-dimensional transistors may be further considered when new future research findings are achieved.…”

Section: Introductionmentioning

confidence: 99%

The impact of channel fin width on electrical characteristics of Si-FinFET

Atalla

Hashim

Ghafar

2022

IJECE

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<span>This paper studies the impact of fin width of channel on temperature and electrical characteristics of fin field-effect transistor (FinFET). The simulation tool multi-gate field effect transistor (MuGFET) has been used to examine the FinFET characteristics. Transfer characteristics with various temperatures and channel fin width (W<sub>F</sub>=5, 10, 20, 40, and 80 nm) are at first simulated in this study. The results show that the increasing of environmental temperature tends to increase threshold voltage, while the subthreshold swing (SS) and drain-induced barrier lowering (DIBL) rise with rising working temperature. Also, the threshold voltage decreases with increasing channel fin width of transistor, while the SS and DIBL increase with increasing channel fin width of transistor, at minimum channel fin width, the SS is very near to the best and ideal then its value grows and going far from the ideal value with increasing channel fin width. So, according to these conditions, the minimum value as possible of fin width is the preferable one for FinFET with better electrical characteristics.</span>

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Graphene‐on‐Silicon Hybrid Field‐Effect Transistors

Fomin

Marín

Pasadas

et al. 2023

Adv Elect Materials

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This continuous downsizing has brought numerous advantages but also relevant challenges, coming hand-in-hand with the conception of novel and varied applications. [3][4][5][6] Among them, biosensing and bioelectronic applications have been successfully explored [7,8] , e.g., employing functionalized specific biomarkers on SiFETs surface, enabling selective label-free detection. [9,10] Silicon has also been utilized for numerous in vitro recordings of electrogenic cells (cardiac or neural) or even in vivo mapping of the whole brain. [11,12] However, it is known to be a bioresorbable material that degrades over time once immersed in saline, thus, suffering from a limited operation time for in vivo applications. [13,14] While silicon still dominates the industrial semiconductor scene, a new material has emerged rather recently, transforming materials science: graphene. Accompanied by other two-dimensional (2D) materials, graphene has already opened new prospects in modern nanoelectronic applications [15][16][17][18] and also holds a great promise for bio-and neuroapplications due to its extraordinary conductivity and good biocompatibility. [19][20][21] In particular, graphene-based FETs (GFETs) and microelectrode arrays (MEAs), both rigid and flexible, have been reported to successfully interface with electrogenic cellsThe combination of graphene and silicon in hybrid electronic devices has attracted increasing attention over the last decade. Here, a unique technology of graphene-on-silicon heterostructures as solution-gated transistors for bioelectronics applications is presented. The proposed graphene-onsilicon field-effect transistors (GoSFETs) are fabricated by exploiting various conformations of channel doping and dimensions. The fabricated devices demonstrate hybrid behavior with features specific to both graphene and silicon, which are rationalized via a comprehensive physics-based compact model which is purposely implemented and validated against measured data. The developed theory corroborates that the device hybrid behavior can be explained in terms of two independent silicon and graphene carrier transport channels, which are, however, strongly electrostatically coupled. Although GoSFET transconductance and carrier mobility are found to be lower than in conventional silicon or graphene field-effect transistors, it is observed that the combination of both materials within the hybrid channel contributes uniquely to the electrical response. Specifically, it is found that the graphene sheet acts as a shield for the silicon channel, giving rise to a nonuniform potential distribution along it, which impacts the transport, especially at the subthreshold region, due to non-negligible diffusion current.

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Electrical characterization of si nanowire GAA-TFET based on dimensions downscaling

Cited by 5 publications

References 23 publications

Characterization of silicon tunnel field effect transistor based on charge plasma

Characterization of silicon tunnel field effect transistor based on charge plasma

The impact of channel fin width on electrical characteristics of Si-FinFET

Graphene‐on‐Silicon Hybrid Field‐Effect Transistors

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