Electrical Measurement of Local Stress and Lateral Diffusion Near Source/Drain Extension Corner of Uniaxially Stressed n-MOSFETs

Hsieh, Chen-Yu; Chen, Ming‐Jer

doi:10.1109/ted.2007.915050

Cited by 16 publications

(5 citation statements)

References 34 publications

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“…where 𝜎 corresponds to the mechanical stress. Hsieh and Chen [15] estimated the relative amplitude of mechanical stress from the measured 𝐼 d(sub) using Eq. ( 2) and…”

mentioning

confidence: 99%

The Enhanced Role of Shallow-Trench Isolation in Ionizing Radiation Damage of Narrow Width Devices in 0.2 μm Partially-Depleted Silicon-on-Insulator Technology

Huang¹,

Bi²,

Peng³

et al. 2013

Chinese Phys. Lett.

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An anomalous total dose effect is observed in narrow-width devices fabricated in a 0.2 𝜇m partially-depleted silicon-on-insulator (SOI) technology. The previous radiation-induced narrow channel effect manifests itself with obvious threshold voltage shift after the transistors are subjected to total dose radiation in bulk technology. Nevertheless, a sharply increasing off-state leakage current dominates the total dose effects in narrow devices of this partially-depleted SOI technology instead of threshold voltage shifts. A radiation-induced positive charge trapping model is introduced to understand this phenomenon. The enhanced role of shallow-trench oxide induced by compressive mechanical stress in narrow devices is discussed in detail in terms of modification of the edge impurity density and charge trapping characteristics, which affect the total dose sensitivity.

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“…where 𝜎 corresponds to the mechanical stress. Hsieh and Chen [15] estimated the relative amplitude of mechanical stress from the measured 𝐼 d(sub) using Eq. ( 2) and…”

mentioning

confidence: 99%

The Enhanced Role of Shallow-Trench Isolation in Ionizing Radiation Damage of Narrow Width Devices in 0.2 μm Partially-Depleted Silicon-on-Insulator Technology

Huang¹,

Bi²,

Peng³

et al. 2013

Chinese Phys. Lett.

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“…It is possible that arsenic diffusion depends more on a vacancy mediated mechanism for a single implant; however, for NMOS transistors involving multiple implants, arsenic diffusion may depend on an interstitial mediated mechanism instead, resulting in arsenic diffusion retardation by compressive stress. The work of Sheu et al 19 has been further confirmed by Hsieh and Chen 10 in 2008. Right now, we are studying a similar situation like Sheu et al and so our opinion is that both boron diffusion in PMOS transistor and arsenic diffusion in NMOS transistor are retarded by compressive stress (Mechanism 1).…”

Section: Discussion On Theory Of Mechanical Stress On Diffusionmentioning

confidence: 82%

“…Several research groups reported on the enhanced boron diffusion through compressive stress that is induced by the nitride spacer 5, 6, shallow trench isolation (STI) 7, Si 1− x Ge x S/D stressor 8, and TiN metal gate 9. At the same time, the retardation of boron has been observed for STI‐induced compressive stress 10, 11, and compressive stressed Si 1− x Ge x layer 12. This work serves to reconcile the conflicting reports on the effects of uniaxial compressive on boron diffusion.…”

Section: Introductionmentioning

confidence: 99%

Mechanism behind the stress‐induced change in boron and arsenic diffusion in silicon devices and its experimental verification

Lau

See

Yang

2011

Physica Status Solidi (a)

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There are contradictory reports regarding the effects of uniaxial compressive stress on boron diffusion in silicon. Some reported on the stress‐induced retardation of boron diffusion, whereas some reported on the stress‐induced enhancement of boron diffusion. This work serves to reconcile the conflicting reports on the effects of shallow trench isolation‐induced compressive stress on boron diffusion in silicon. We propose that there are two opposing mechanisms that affect the strain‐induced change in boron diffusion. Mechanism 1, which is related to the strain‐induced reduction in the silicon lattice constant, will lead to a retardation of the boron diffusion of the S/D extension implants. Mechanism 2, which is related to the formation of transient dislocations in silicon during the ramping up period of the S/D annealing, will lead to an enhancement of boron diffusion of the S/D extension implants. The interactions between the two opposing mechanisms would affect the on current versus S/D overhang characteristics as well as the off current versus S/D overhang characteristics. Similar theory can be extended to arsenic diffusion.

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“…Flash annealing and laser annealing have been proposed as replacement to conventional spike annealing. 3,4) On the other hand, the diffusion coefficient of the dopant has been observed to be strongly affected by either uniaxial stress [5][6][7][8][9] or biaxial stress engineering. [10][11][12] A thermodynamic model of dopant diffusion on the Si substrate under hydrostatic or nonhydrostatic stress has been developed to explain point defect behavior.…”

mentioning

confidence: 99%

“…The change in dopant diffusivity depends on the stress level in the substrate for different species. [5][6][7][8][9]13) The I on -I off behavior as well as the stress simulation prediction of spacer stress engineering is without obvious improvement. According to the technology computer aided design (TCAD) stress simulation, the stress at the gate edge is abruptly increased by a factor of 2.2 for the compressive spacer and 2.5 for the tensile spacer when the depth of the S/D extension junction is reduced from 40 to 5 nm, as shown in Fig.…”

mentioning

confidence: 99%

An Efficient Threshold Voltage Control in Complementary Metal–Oxide–Semiconductor Field Effect Transistor Using Spacer Stress Engineering

Huang¹,

Chen

Lee³

2010

Jpn. J. Appl. Phys.

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In this work, we have demonstrated an efficient method to control threshold voltage in complementary metal–oxide–semiconductor field effect transistor (CMOSFET) using spacer stress technology compatible with a very-large-scale integration (VLSI) process. Consequently, the threshold voltage of the device could be shifted by 180 mV for n-type FETs (n-FETs) with a tensile-stressed SiN spacer and by 20 mV for p-type FETs (p-FETs) with a compressively stressed oxide spacer. From a theoretical thermodynamics model as well as reported experimental data, we demonstrated that spacer stress could play an important role on threshold voltage control due to altering the diffusivities of dopants in silicon.

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Electrical Measurement of Local Stress and Lateral Diffusion Near Source/Drain Extension Corner of Uniaxially Stressed n-MOSFETs

Cited by 16 publications

References 34 publications

The Enhanced Role of Shallow-Trench Isolation in Ionizing Radiation Damage of Narrow Width Devices in 0.2 μm Partially-Depleted Silicon-on-Insulator Technology

The Enhanced Role of Shallow-Trench Isolation in Ionizing Radiation Damage of Narrow Width Devices in 0.2 μm Partially-Depleted Silicon-on-Insulator Technology

Mechanism behind the stress‐induced change in boron and arsenic diffusion in silicon devices and its experimental verification

An Efficient Threshold Voltage Control in Complementary Metal–Oxide–Semiconductor Field Effect Transistor Using Spacer Stress Engineering

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