Electrical Model of Different Architectures of through Silicon Capacitors for High Frequency Power Distribution Network (PDN) Decoupling Operations

Dieng, Khadim; Bermond, C.; Artillan, Philippe; Guiller, Olivier; Lacrevaz, T.; Joblot, S.; Houzet, Grégory; Farcy, A.; Lamy, Yann; Flechet, B.

doi:10.1109/ectc.2016.335

Cited by 5 publications

(1 citation statement)

References 12 publications

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“…Using standard full-wave finite element analysis (FEA) software to model complete structure of hundreds of TSCs would necessitate huge resources and computing time, and such simulations seem to be unreachable in some cases. To overcome this issue and to be able to quantify the parasitic elements of large matrices of TSC, one developed two modeling methods for two architectures of TSC [8]. Those modeling methods, based on a segmented approach, make use of 2-D/3-D parasitic extraction software for the modeling of each part of the structure.…”

Section: Modeling and Frequency Performance Analysis Of Through Silicmentioning

confidence: 99%

Modeling and Frequency Performance Analysis of Through Silicon Capacitors in Silicon Interposers

Dieng

Artillan

Bermond

et al. 2017

IEEE Trans. Compon., Packag. Manufact. Technol.

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The feasibility of cointegration of new capacitors, named "through silicon capacitors" (TSCs) with "through silicon vias" in silicon interposers has recently been demonstrated. Two architectures of TSC are extensively investigated in this paper: "axial TSC" whose electrodes are connected on either sides of the silicon interposer and "radial TSC" with electrodes both connected to the metal layers of the back end of line. A general modeling method based on distributed cell segmentation is proposed for both architectures. Validation is performed by measurements from 1 kHz to 40 GHz (above the resonance frequency of the components). A comparative study between radial and axial architectures is performed, leading to the prediction of the performances of those new components. Finally, design rules are established for future integration for power delivery networks decoupling applications.

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Section: Modeling and Frequency Performance Analysis Of Through Silicmentioning

confidence: 99%

Modeling and Frequency Performance Analysis of Through Silicon Capacitors in Silicon Interposers

Dieng

Artillan

Bermond

et al. 2017

IEEE Trans. Compon., Packag. Manufact. Technol.

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A 56 Gbps I/O Interface Design with Exact Power Source Simulation: Total I/O Circuit Design with over 28 GHz from Driver to Receiver Device Models

Ogawa¹,

Iguchi²,

Wada

et al. 2018

2018 IEEE 68th Electronic Components and Technology Conference (ECTC)

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3D Electromagnetic Simulation and Modeling for DTCO of Decoupling High-Density Capacitor in Silicon Interposer for HPC Applications

Jacquinot,

Pluchart,

Rothan

et al. 2024

2024 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

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Electrical Model of Different Architectures of through Silicon Capacitors for High Frequency Power Distribution Network (PDN) Decoupling Operations

Cited by 5 publications

References 12 publications

Modeling and Frequency Performance Analysis of Through Silicon Capacitors in Silicon Interposers

Modeling and Frequency Performance Analysis of Through Silicon Capacitors in Silicon Interposers

A 56 Gbps I/O Interface Design with Exact Power Source Simulation: Total I/O Circuit Design with over 28 GHz from Driver to Receiver Device Models

3D Electromagnetic Simulation and Modeling for DTCO of Decoupling High-Density Capacitor in Silicon Interposer for HPC Applications

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