Electrical, optical and fluidic through-silicon vias for silicon interposer applications

Abstract

Modern high-performance computing systems and data centers are implemented as many-core server systems. Current state of the art data centers have server racks with pluggable boards where each board has many multi-core processors and memory units. These boards are connected via electrical or optical cables. In such systems, communication bandwidth between the high-speed microprocessor cores and the memory is limited. To leverage full performance of these powerful chips, it is required to provide high memory bandwidth as well as effective power delivery and heat removal solutions. To address these challenges in high performance computing systems, we present a 3D packaging solution that includes a novel silicon interposer with electrical, optical, and fluidic (trimodal) interconnects and through-silicon vias (TSVs). The electrical TSVs in the silicon interposer enable power and signal delivery from motherboard to chips stacked on top of the interposer. The optical TSVs in the silicon interposer can provide ultra-high bandwidth communication between chips on different silicon interposers through motherboard level optical links. The fluidic TSVs enable a coolant to be routed from the motherboard to the chips on the silicon interposer. We have fabricated and characterized polymer-clad electrical TSVs (for low stress) with diameter that meets ITRS projections for high-performance computing systems. Using the same polymer used for the cladding of electrical TSVs, we have fabricated and characterized optical TSVs adjacent to electrical TSVs. Spin coating of the photodefinable polymer for electrical and optical TSVs is done in single step. Fabrication of fluidic TSVs can be done using the same cladding as that of the polymer-clad electrical TSVs without electroplating the copper. This leaves behind an empty polymer-clad via which can be used as a fluidic TSV. I: IntroductionThe performance of a processor is commonly measured as the number of instructions it processes per unit time. For high performance and utilization of the processor, the rate at which memory supplies instructions and data to the processor must match with the rate at which the processor is processing them. With the migration towards multi-core and multi-threading, the memory gap problem becomes more acute since now multiple processors on a single chip will increase the memory bandwidth demand. Thus, all the performance benefits of this processor cannot be fully leveraged because memory speeds are much slower compared to the processor speed [1, 2]. Fig. 1 shows scaling in processor frequencies and the memory speed over the past years. To solve this problem, we must improve the memory throughput and reduce the memory latency which includes interconnect delay in addition to memory access delay. This was quantified with analytical simulations to determine the effect of increased memory bandwidth on a processor chip, and we see that performance increase is proportional to the available memory bandwidth. Fig. 2 shows that throughput increases from 96 BIPS (bi...

Towards ultrasonic through-silicon vias (UTSV)

“…At distances greater than the natural focus, diffraction effects begin to come into play and the beam begins broadening and the signal begins to suffer from 1/r 2 losses. From (2) and (3), it can be seen that as the dimensions of the transducer shrinks, the Fresnel zone length gets shorter and the main lobe gets wider, and thus the acoustic waves excited by the transducer will experience more diffraction loss than for a larger transducer.…”

“…The dominant 3D interconnect in use in 3DICs today is the through silicon via, which is a physical wire interconnect through a thinned silicon wafer. In addition to TSVs, other types of 3D interconnects for communication are capacitive, inductive, and optical links [1][2]. We propose a new type of 3D interconnect -the ultrasonic through silicon via (UTSV).…”

Novel photodefined polymer-embedded vias for silicon interposers

“…The performance improvement from complementary metaloxide-semiconductor (CMOS) scaling has been reducing due to a disparity between the rapid rate of CMOS scaling and the slower rate of the development of silicon ancillary technologies [1,2]. To cope with this challenge, 2.5-dimensional (2.5D) and 3-dimensional (3D) interconnection of integrated circuits (ICs) is currently being widely explored to obtain high-bandwidth chip-to-chip communication at lower power consumption [1][2][3][4][5][6]. Silicon interposers with high-density and fine-pitch wiring and through-silicon vias (TSVs) have been shown as a promising substrate technology to support and interconnect multiple single chips as well as 3D chip stacks [4][5][6].…”

Heterogeneous 2D/3D photonic integrated microsystems

“…Such 3D PICs can also be realized by wafer bonding of 2D PICs of similar 31 or dissimilar 32 materials while employing vertical couplers utilizing inverse taper waveguides for interlayer optical coupling. The interlayer optical coupling can also exploit photonic vias analogous to electrical TSVs, and a recent work 33 has realized fabrication of photonic, electronic, and fluidic through-silicon vias in the same chip.…”