Electrical Properties of Al[sub 2]O[sub 3]/ZrO[sub 2]/Al[sub 2]O[sub 3] Gate Stack in p-Substrate Metal Oxide Semiconductor Devices

Abstract

The electrical properties of the Al 2 O 3 /ZrO 2 /Al 2 O 3 gate dielectric stack are investigated in p-substrate metal oxide semiconductor capacitors and transistors. It is found that the leakage current through the gate stack shows different temperature dependence in low-and high-field regions. This is explained by the different conduction mechanisms at the low and high gate bias. The leakage current is mainly due to tunneling in the low field region, while both tunneling and Frenckel-Poole hopping are involved in the conduction in the high-field region. After constant current stress, both increase of leakage current and positive charge generation are observed. It is also found that the breakdown always occurs in the source/drain overlapped region after uniform voltage stress of the gate stack. The weaker overlapped region is related to ion implantation-induced crystal defects or high doping concentration in the source/drain regions.

Defect Generation for a Hydrated Layer and Thermal Stability Based on Ba0.7Sr0.3TiO3/SiO2 as H+ Sensitive Layer in Ion-Sensitive Field-Effect Transistor Devices

“…This can be explained by assuming the release of hydrogen close to the Si/SiO 2 interface where the hopping of H þ induces positive charges at the site of interface state densities. 21,22) The band diagram is shown in Figs. 5(a) and 5(b).…”