Electrical properties of SiGe nanowire following fluorine/nitrogen plasma treatment

Chang, Kow–Ming; Chen, Chu Feng; Lai, Ching-Yi; Kuo, Po Shen; Chang, Tai Yuan

doi:10.1016/j.apsusc.2013.11.047

Cited by 2 publications

(2 citation statements)

References 19 publications

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“…The defects in nanowires may fundamentally alter charge transport processes. ,− Specifically, the defects in the form of twin planes and stacking faults can be controllably generated in as-grown nanowires, for example, in the III–V nanowires with periodic twin interfaces between alternating ZB and WZ polytype structures. − Charge transport through such twin interfaces or stacking faults is usually determined by different polytype structure, energy gap, and k -point in the two-dimensional Brillouin zone. For instance, the WZ segment in the GaAs ⟨111⟩ nanowire possesses a larger band gap than the ZB segment, which leads to a reduced conductance in the twin GaAs nanowire .…”

Section: Fundamental Electronic Properties Of Single Nanowire Transis...mentioning

confidence: 99%

Nanowire Electronics: From Nanoscale to Macroscale

et al. 2019

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Semiconductor nanowires have attracted extensive interest as one of the best-defined classes of nanoscale building blocks for the bottom-up assembly of functional electronic and optoelectronic devices over the past two decades. The article provides a comprehensive review of the continuing efforts in exploring semiconductor nanowires for the assembly of functional nanoscale electronics and macroelectronics. Specifically, we start with a brief overview of the synthetic control of various semiconductor nanowires and nanowire heterostructures with precisely controlled physical dimension, chemical composition, heterostructure interface, and electronic properties to define the material foundation for nanowire electronics. We then summarize a series of assembly strategies developed for creating well-ordered nanowire arrays with controlled spatial position, orientation, and density, which are essential for constructing increasingly complex electronic devices and circuits from synthetic semiconductor nanowires. Next, we review the fundamental electronic properties and various single nanowire transistor concepts. Combining the designable electronic properties and controllable assembly approaches, we then discuss a series of nanoscale devices and integrated circuits assembled from nanowire building blocks, as well as a unique design of solution-processable nanowire thin-film transistors for high-performance large-area flexible electronics. Last, we conclude with a brief perspective on the standing challenges and future opportunities.

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Section: Fundamental Electronic Properties Of Single Nanowire Transis...mentioning

confidence: 99%

Nanowire Electronics: From Nanoscale to Macroscale

et al. 2019

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“…The other challenge about SiGe Fin channel is that it has relatively high interface trap charge (N it ) at the interfacial layer (IL)/SiGe channel due to the undesired GeO x formation [10]. The passivation techniques of SiGe layer, such as Si-cap, O 3 low temperature oxidation, selective GeO x -Scavenging, and fluorine/nitrogen plasma treatment, have been studied and the experimental demonstration on low-N it SiGe gate stack have been reported [11][12][13][14][15]. However, these passivation techniques may have compatibility problems with a state-ofthe-art FinFET.…”

Section: Introductionmentioning

confidence: 99%

Four-Period Vertically Stacked SiGe/Si Channel FinFET Fabrication and Its Electrical Characteristics

Zhao

Cheng

et al. 2021

Nanomaterials

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In this paper, to solve the epitaxial thickness limit and the high interface trap density of SiGe channel Fin field effect transistor (FinFET), a four-period vertically stacked SiGe/Si channel FinFET is presented. A high crystal quality of four-period stacked SiGe/Si multilayer epitaxial grown with the thickness of each SiGe layer less than 10 nm is realized on a Si substrate without any structural defect impact by optimizing its epitaxial grown process. Meanwhile, the Ge atomic fraction of the SiGe layers is very uniform and its SiGe/Si interfaces are sharp. Then, a vertical profile of the stacked SiGe/Si Fin is achieved with HBr/O2/He plasma by optimizing its bias voltage and O2 flow. After the four-period vertically stacked SiGe/Si Fin structure is introduced, its FinFET device is successfully fabricated under the same fabrication process as the conventional SiGe FinFET. And it attains better drive current Ion, subthreshold slope (SS) and Ion/Ioff ratio electrical performance compared with the conventional SiGe channel FinFET, whose Fin height of SiGe channel is almost equal to total thickness of SiGe in the four-period stacked SiGe/Si channel FinFET. This may be attributed to that the four-period stacked SiGe/Si Fin structure has larger effective channel width (Weff) and may maintain a better quality and surface interfacial performance during the whole fabrication process. Moreover, Si channel of the stacked SiGe/Si channel turning on first also may have contribution to its better electrical properties. This four-period vertically stacked SiGe/Si channel FinFET device has been demonstrated to be a practical candidate for the future technology nodes.

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Electrical properties of SiGe nanowire following fluorine/nitrogen plasma treatment

Cited by 2 publications

References 19 publications

Nanowire Electronics: From Nanoscale to Macroscale

Nanowire Electronics: From Nanoscale to Macroscale

Four-Period Vertically Stacked SiGe/Si Channel FinFET Fabrication and Its Electrical Characteristics

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