Electrical stress in CdS thin film transistors using HfO2 gate dielectric

Abstract

During thin film transistor (TFT) operation, gate dielectric is under a bias stress condition. In this work, bias stress effect for CdS TFT using HfO2 as gate dielectric is analyzed. Threshold voltage, Ion/Ioff ratio, and subthreshold slope were studied in order to understand changes produced at the dielectric semiconductor interface. We observed that threshold voltage shift is related with negative charge trapping in the dielectric/semiconductor interface and for this phenomenon we propose a trapping charge model. Finally, the TFT output characteristic was modeled considering a shift in the threshold voltage for each gate voltage curve.

Bias stress study of Metal-Insulator-Semiconductor structures with pulsed laser deposited InGaZnO on atomic layer deposited HfO2

“…Since V FB largely determines the subthreshold voltage (V Th ) on TFTs, if bias stress instability is manifested as a shift of V Th , then V FB will provide a direct measurement of changes in device performance associated with either charge trapping at the dielectric/semiconductor interface or charge injection into gate insulator material [1,2,9,12]. After the second voltage sweep, the C-V characteristic stabilizes, as shown in Fig.…”

“…First, C-V curves were measured through ten consecutive voltage sweeps from −5 V to 15 V, in order to detect if there is a bias stress effect produced by the variations in the characteristic parameters of the MIS capacitor due to charge trapping and/or new trap states created on each subsequent measurement [9]. Fig.…”

“…On the other hand, reliability is one of the concerns regarding to AOS-TFTs because of degradation of the device performance commonly associated to a threshold voltage shifts by bias or constant current stress conditions [3,5,9]. Some woks have previously reported TFTs fabricated with IGZO as active layer and gate dielectric films of high-k HfO 2 , both layers were deposited by Radio-Frequency (RF) magnetron sputtering, showing suitable electrical properties for transparent and flexible electronics [10,11].…”

“…Moreover, by using gate insulating layers with high dielectric constants that allow to reduce tunneling leakage currents, as well as, the operating voltage and the subthreshold swing of the TFT. Thus, hafnium oxide (HfO 2 ) is being highly considered as gate dielectric material [2,3,6,9].…”

Decreasing the V th shift of InGaZnO thin-film transistors under positive and negative bias stress using SU-8 as etch-stop and passivation layer

“…The mobility does not change as a function of the stress time with values around 12.5, 12 and 9.5 cm 2 V −1 s −1 for an L of 40, 60 and 80 µm, respectively. The amount of the interface trap density (D it ) is related to the quality of the semiconductor/dielectric interface which is associated to the variation of the subthreshold slope [38,39]. The change in D it (∆D it ) is calculated using the sub-threshold slope before and after degradation for every stress time [40]:…”