Electrically Active Interface Defects in the (100)Si/SiOx/HfO2/TiN System: Origin, Instabilities and Passivation

Abstract

An analysis of the origin and passivation of interface states in (100)Si/SiO x /HfO 2 /TiN capacitor structures is presented. For highk gate/metal gate capacitors which exhibit relatively high interface state densities (> 1x10 11 cm -2 ) the dominant interfacial defects are silicon dangling bond (P bo ) centres. For (100)Si/SiO x /HfO 2 /TiN capacitors which experience no high temperature thermal budget following HfO 2 /TiN gate formation (T<600 o C), the devices exhibit instabilities, where the interface state densities are modified during electrical measurements. The origin of this instability is studied. The response of the interface state density to rapid thermal annealing (30s) in N 2 over the temperature range 600-900 o C is presented. In addition, results are presented for interface state passivation in forming gas (0.5H 2 /0.95N 2 ) from 350-550 o C for (100)Si/SiO x /HfO 2 /TiN gate stacks with no post deposition annealing following TiN gate formation and for devices following a 900 o C, 30s N 2 RTA.

Decreasing Interface Defect Densities via Silicon Oxide Passivation at Temperatures Below 450 °C

“…Therefore, the high-quality HfO 2 /SiO x /Si stacks for transistors are often postannealed above 700 °C. [7][8][9][10][11][12]46,47 The gained benefit of this HT postannealing arises most likely from an increased degree of crystallization of SiO x , because HT treatments have been found to provide a crystalline interface layer for SiO x /Si systems. 48−57 Interfacial crystallization leads to a natural decrease in the density of point defects, as compared to the corresponding amorphous (or disordered) interface.…”

“…Interface oxides, formed at LT, are typically amorphous or highly disordered. Therefore, the high-quality HfO 2 /SiO x /Si stacks for transistors are often postannealed above 700 °C. − ,, The gained benefit of this HT postannealing arises most likely from an increased degree of crystallization of SiO x , because HT treatments have been found to provide a crystalline interface layer for SiO x /Si systems. − Interfacial crystallization leads to a natural decrease in the density of point defects, as compared to the corresponding amorphous (or disordered) interface. It is essential to note that high-quality transistor HfO 2 /SiO x /Si interfaces are still subsequently hydrogen passivated, in addition to the HT treatments (i.e., combination of HT annealing and hydrogen exposure).…”

Interface Defects in HfO[sub 2], LaSiO[sub x], and Gd[sub 2]O[sub 3] High-k/Metal–Gate Structures on Silicon

“…The initial samples analyzed in this work are intentionally focused on high-k/metal-gate samples which experience no H 2 /N 2 annealing following gate stack formation to allow an examination of the dominant interface defects prior to passivation by hydrogen. [18][19][20][21] The final section of the paper considers the impact of H 2 /N 2 annealing on the interface defect density.…”

“…Such observations have been reported for a range of high-k thin films, including ZrO 2 , HfO 2 , La 2 O 3 , LaAlO 3 , Lu 2 O 3 , Dy 2 O 3 , and other high-k MIS structures. [21][22][23][24][25][26][27][28][29][30] In the case of the Si͑100͒/SiO x /HfO 2 /metal-gate system, a range of experimental results has now been published [14][15][16][17]19,20 which indicate that the physical origin of the interface defect underlying the frequency-dependent distortion in the C-V response is the P b0 ͑sili-con dangling bond͒, center characteristic of the Si͑100͒/SiO 2 interface. In this paper, the results in Ref.…”

“…In this paper, the results in Ref. 21 and 31 for the Si͑100͒/SiO x /HfO 2 system are extended to provide a comparative analysis of interface defects for HfO 2 , LaSiO x , and Gd 2 O 3 metal gate MIS structures. Gadolinium-and lanthanum-based oxides were selected based on experimental results indicating promising electrical data 2,32,33 and on empirical relationships for k values and energy band offsets.…”