Semiconductor manufacturers and researchers have recently revealed that under specific bipolar gate switching conditions SiC MOSFETs exhibit parameter drift dynamics different from those typically observed in static qualification stress tests. In response to this finding, we present an approach for assessing the worst-case drift of data-sheet-relevant electrical parameters in a simple and transparent manner for a large variety of application profiles. We also introduce an empirical model that may explain the drift dynamics observed under gate switching stress; and discuss a recently developed interface characterization technique that has the potential to reveal the nature of point defects at the SiC/SiO2 interface presumably related to the gate switching instability in SiC MOSFETs.