Electrolessly deposited diffusion barriers for microelectronics

O’Sullivan, E. J.; Schrott, A. G.; Paunović, Milan; Sambucetti, C.J.; Marino, J. R.; Bailey, Peter J.; Kaja, S.; Semkow, K. W.

doi:10.1147/rd.425.0607

Cited by 145 publications

(77 citation statements)

References 2 publications

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“…12 Electroless NiP, NiB, CoP, and NiCoP deposition films have been proposed as the barrier/cladding materials for Cu metallization and these electroless barriers were effective for Cu up to 450°C. [13][14][15] Kohn et al [16][17][18][19] and Shacham-Diamand et al 11,20 added the refractory metals in the electroless CoP deposition to improve the electroless barrier efficiency. Electrolessly deposited Co 0.9 W 0.02 P 0.08 thin films in the CoWP/Cu/CoWP/Co (sputter)/Ti (sputter)/SiO 2 /Si stacked samples can significantly promote the failure temperature up to 500°C by the blocking effect of W and P enriching at the cobalt grain boundary.…”

Section: Introductionmentioning

confidence: 99%

Electroless CoWP as a Diffusion Barrier between Electroless Copper and Silicon

Tsai

Liu

et al. 2007

Journal of Elec Materi

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In this work, an electroless CoWP film deposited on a silicon substrate as a diffusion barrier for electroless Cu and silicon has been studied. Four different Cu 120 nm/CoWP/Si stacked samples with 30, 60, 75, and 100 nm electroless CoWP films were prepared and annealed in a rapid thermal annealing (RTA) furnace at 300°C to 800°C for 5 min. The failure behavior of the electroless CoWP film in the Cu/CoWP/Si sample and the effect of CoWP film thickness on the diffusion barrier properties have been investigated by transmission electron microscopy (TEM), scanning electron microscopy (SEM), X-ray diffraction (XRD), and sheet resistance measurements. The composition of the electroless CoWP films was 89.4 at.% Co, 2.4 at.% W, and 8.2 at.% P, as determined by energy dispersive X-ray spectrometer (EDS). A 30 nm electroless CoWP film can prevent copper penetration up to 500°C, and a 75 nm electroless CoWP film can survive at least up to 600°C. Therefore, increasing the thickness of electroless CoWP films effectively increases the failure temperature of the Cu/CoWP/Si samples. The observations of SEM and TEM show that interdiffusion of the copper and cobalt causes the failure of the electroless CoWP diffusion barriers in Cu/CoWP/Si during thermal annealing.

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Section: Introductionmentioning

confidence: 99%

Electroless CoWP as a Diffusion Barrier between Electroless Copper and Silicon

Tsai

Liu

et al. 2007

Journal of Elec Materi

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“…Electroless cobalt-phosphorous alloys [Co(P)] serving as diffusion barriers of Cu and polyimide dielectrics in multilayer microelectronic structures (Received October 28, 2005; accepted February 13,2006) have been studied by O'Sullivan et al 10 Their investigation showed that electroless Co(P) is highly effective in inhibiting Cu diffusion at elevated temperatures, even at Co(P) thickness as low as 50 nm. The electroless Co(P) also exhibited a better diffusion-barrier effectiveness in comparison with Ni(P) and pure metals (Co, Ni).…”

Section: Introductionmentioning

confidence: 99%

Investigation of electroless cobalt-phosphorous layer and its diffusion barrier properties of Pb-Sn solder

Liang

Yen

Hsieh

2006

Journal of Elec Materi

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The capability of a cobalt-phosphorous [Co(P)] layer, which was grown via the electroless plating process, to serve as the diffusion barrier of lead-tin (PbSn) solder was investigated in this work. The Auger electron spectroscopy (AES) and energy dispersive spectrometry (EDX) indicated that the phosphorous contents in Co(P) films decrease with increasing film thickness and that the average contents are no less than 8.7 at.% for the specimens prepared in this work. X-ray diffraction in conjunction with composition analyses revealed that the electroless Co(P) layer was a mixture of amorphous and nanocrystalline structures; however, the AES depth profile and subsequent analyses indicated that the first-formed Co(P) layer should be amorphous because it contains as much as 18 at.% P. This implied a good barrier capability for electroless Co(P) because, as revealed by EDX line scan, the Sn and Cu atoms could not penetrate the Co(P) layer after the PbSn/Cu/Co(P)/Cu/Ti/Si sample was subjected to annealing at 250°C in a forming gas ambient for 24 h. The fact that Sn and Cu underlayers could not penetrate the Co layer after such a liquid-state annealing step was evidence that the Co(P) layer may simultaneously serve as a diffusion-barrier interlayer dielectric and as an under-bump metallization for flip-chip copper (Cu) ICs.

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“…With an increasing degree of integration, difficulties in uniform formation of thin films have appeared in fine-patterned structures with high aspect ratios, due to the intrinsic limitation of the sputtering technique itself. Recently, a process of fabricating a barrier layer by electroless deposition has been proposed [18][19][20][21]. Electroless deposition has several advantages, compared with the dry method, such as its simplicity of operation and its low cost.…”

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“…In particular, it is attractive for producing uniform deposits independent of the size and geometry of the structure, which could help us overcome the above-mentioned problem on coverage. However, the electroless deposition of barrier layers usually requires the sputtering process of seeds to initiate its reaction [18][19][20][21], resulting in a lessening in the advantage of the electroless deposition method. We have proposed a concept for all-wet Cu wiring fabrication technology, as shown in Fig.…”

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confidence: 99%