Electrolyte‐Gated Transistor Array (20 × 20) with Low‐Programming Interference Based on Coplanar Gate Structure for Unsupervised Learning

Abstract

Compute‐in‐memory (CIM) is a pioneering approach using parallel data processing to eliminate traditional data transmission bottlenecks for faster, energy‐efficient data handling. Crossbar arrays with two‐terminal devices such as memristors and phase‐change memory are commonly employed in CIM, but they encounter challenges such as leakage current and increased power usage. Three‐terminal transistor arrays have potential solutions, yet large‐scale electrolyte‐gated transistors (EGTs) demonstrations are uncommon due to compatibility issues with existing photolithography processes. Herein, a 20 × 20 EGTs array is designed using indium‐gallium‐zinc‐oxide as the semiconductor channel and polyacrylonitrile (PAN) doped with C2F6LiNO4S2 as the electrolyte. Each transistor unit in the array can serve as a synapse, exhibiting a large conductance range, low energy consumption (6.984 fJ) for read–write operations, excellent repeatability, and quasilinear update characteristics. It has been confirmed that the EGTs array not only enables precise device programming but also virtually eliminates signal interference between neighboring devices during the programming process. Using 54 transistors in the EGTs array, unsupervised learning with a winner‐takes‐all neural network is successfully demonstrated. After 50 training iterations, the neural network achieves perfect 100% accuracy in classifying test‐set letters. The work demonstrates the potential of EGTs for constructing large‐scale integration synaptic array toward efficient computing architectures.