Electromagnetic Fault Injection as a New Forensic Approach for SoCs

Abstract

Smartphones have a complex hardware and software architecture. Having access to their full memory space can help solve judicial investigations. We propose a new privilege escalation technique in order to access hidden contents and execute sensitive operations. While classical forensic tools mostly exploit software vulnerabilities, it is based on a hardware security evaluation technique. Electromagnetic fault injection is such a technique usually used for microcontrollers or FPGA security characterization. A security function running at 1.2 GHz on a 64-bit SoC with a Linux-based OS was successfully attacked. The Linux authentication module uses this function to verify the password correctness by comparing two hash values. Hence, this work constitutes a step towards smartphones privilege escalation through electromagnetic fault injection. This approach is interesting for addressing forensic issues on smartphones.

Resistance of Isogeny-Based Cryptographic Implementations to a Fault Attack

“…The reader might wonder why the best success rate is only 0.62% experimentally while the theoretical success rate of the attack is around 50% as seen in Remark 3. This is due to the low repeatability of electromagnetic fault injection [10]: a lot of attempts at altering the algorithm's execution does not induce faults, or at least not in a way that enables us to perform the attack (e.g. a reboot).…”

“…Before performing real-life electromagnetic fault attacks, we decided to simulate these attacks using software only. Indeed, fault injection attacks are long and complex to carry out [10], thus we chose to validate the attack with a simulation before the laboratory experiments. There were two steps: rst, we used Sagemath [26] to simulate fault injection and to recover the secret isogeny with an implementation of Algorithm 2 and then we emulated the target in C and injected the fault by debugging, while recovering the secret with the same Sage implementation of Algorithm 2.…”

“…The target is a system on chip (SoC) equipped with four ARM Cortex-A53 cores and including a Yocto Linux operating system. While it is dicult to fault a chosen instruction because of a poorly predictable latency of execution in SoCs [10], we have seen in Section 3 and with the simulation in Section 4.1 that we only need to fault the beginning of the key generation and do not need to choose precisely the time for the fault injection. Thus we can expect a successful attack on such a target.…”

“…During our campaign, the probe does not move and the pulse width is set at 6 ns. This position and the width are propitious for fault injection according to [10]. The amplitude varies from 300 to 360 V with a 20 V step and the delay between the start of the public key generation and the fault injection varies from 100 to 600 ns with a 20 ns step.…”

EM Fault Model Characterization on SoCs: From Different Architectures to the Same Fault Model

“…The drawback of this computational power is a complex hardware layout which is, for now, lacking security analysis, in particular, regarding hardware attacks. However, some recent works have demonstrated that these attacks are efficient to lower the security of modern SoCs [5], [11], [12], [13]. Therefore, we believe it is important to understand the underlying effect induced by the proposed perturbations to be able to measure their impact and design adapted countermeasures.…”