2010
DOI: 10.2320/matertrans.m2009367
|View full text |Cite
|
Sign up to set email alerts
|

Electromigration Behavior of through-Si-via (TSV) Interconnect for 3-D Flip Chip Packaging

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

0
1
0

Year Published

2017
2017
2017
2017

Publication Types

Select...
1

Relationship

0
1

Authors

Journals

citations
Cited by 1 publication
(1 citation statement)
references
References 21 publications
0
1
0
Order By: Relevance
“…8 The use of three-dimensional (3D) packaging through-silicon via (TSV) technology allows a high density of vertical interconnects, unlike 2D packing, as shown in Figure 1. 3D TSV ICs have the following advantages: (1) reduced connection lengths, and thus smaller parasitic capacitance, inductance, and resistance; (2) high-speed low-power interconnects; and (3) a combination of monolithic and multifunctional integration.…”
mentioning
confidence: 99%
“…8 The use of three-dimensional (3D) packaging through-silicon via (TSV) technology allows a high density of vertical interconnects, unlike 2D packing, as shown in Figure 1. 3D TSV ICs have the following advantages: (1) reduced connection lengths, and thus smaller parasitic capacitance, inductance, and resistance; (2) high-speed low-power interconnects; and (3) a combination of monolithic and multifunctional integration.…”
mentioning
confidence: 99%