Electromigration Failure Mechanism and Lifetime Expectation for Bi-Modal Distribution in Cu/Low-k Interconnect

Wee, Y.J.; Kim, A.T.; Lee, Jung Eun; Maeng, Jae Yeol; Choi, W.-H.; Nam, Sang-Wan; Lee, Seungjin; Lee, Kyoung Woo; Kim, Jaehak; Jun, Keeyoung; Choi, Seung Man; Choo, Jaeouk; Heo, Jungshik; Shin, Hong Jae; Lee, Nae In

doi:10.1109/iitc.2007.382343

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“…The electromigration (EMG) phenomenon is becoming more and more critical for chip reliability since the 32 nm technology node [1][2][3]. In order to anticipate this reliability issue, EMG checks are done at design level based mainly on the electrical parameters [4].…”

Section: Introductionmentioning

confidence: 99%

Power grid redundant path contribution in system on chip (SoC) robustness against electromigration

Ouattara

Doyen

Ney

et al. 2014

Microelectronics Reliability

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Section: Introductionmentioning

confidence: 99%

Power grid redundant path contribution in system on chip (SoC) robustness against electromigration

Ouattara

Doyen

Ney

et al. 2014

Microelectronics Reliability

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Analysis of electromigration induced early failures in Cu interconnects for 45nm node

Arnaud

Cacho

Doyen

et al. 2010

Microelectronic Engineering

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Redundancy method to assess electromigration lifetime in power Grid design

Ouattara¹,

Doyen²,

Ney³

et al. 2013

2013 IEEE International Interconnect Technology Conference - IITC

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The tendency of semiconductor market to increase component density in small chip leads to reliability issues such as Electromigration (EM). This phenomenon becomes critical in deep submicron design technology. In this paper we assess chip power grid lifetimes by taking into account redundant paths contribution in case of EM degradation. The application of this method for wire lifetime validation of a 32nm microprocessor has reduced significantly wires susceptible to EM given by simulation tools.

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Electromigration Failure Mechanism and Lifetime Expectation for Bi-Modal Distribution in Cu/Low-k Interconnect

Cited by 3 publications

References 1 publication

Power grid redundant path contribution in system on chip (SoC) robustness against electromigration

Power grid redundant path contribution in system on chip (SoC) robustness against electromigration

Analysis of electromigration induced early failures in Cu interconnects for 45nm node

Redundancy method to assess electromigration lifetime in power Grid design

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