Electromigration reliability enhancement via bus activity distribution

Dasgupta, A.; Karri, R.

doi:10.1109/dac.1996.545600

Cited by 12 publications

(3 citation statements)

References 8 publications

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“…The physical design aspect of EM has been extensively researched. Numerous studies [7,10,21] have analyzed the impact of EM on various types of interconnect materials in various processes, temperatures, and voltage conditions. The prevailing physical solution is to increase the width of the wires, which, as shown in Equation ( 2), extends MTF and ultimately mitigates EM effects.…”

Section: Prior Work On Electromigrationmentioning

confidence: 99%

“…Until now, the emphasis in common IS design flows has been on improving the implementation and design flow of ICs [1,2,[7][8][9][10][11][12][13] to address EM-related issues, with few studies proposing microarchitectural solutions. In this work, we offer a new microarchitecture that enhances the reliability of the memory hierarchy in modern microprocessors by reducing the impact of RMS-EM and simplifying their design efforts while offering a significant lifetime extension.…”

Section: Introductionmentioning

confidence: 99%

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Electromigration-Aware Memory Hierarchy Architecture

Gabbay

Mendelson

2023

JLPEA

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New mission-critical applications, such as autonomous vehicles and life-support systems, set a high bar for the reliability of modern microprocessors that operate in highly challenging conditions. However, while cutting-edge integrated circuit (IC) technologies have intensified microprocessors by providing remarkable reductions in the silicon area and power consumption, they also introduce new reliability challenges through the complex design rules they impose, creating a significant hurdle in the design process. In this paper, we focus on electromigration (EM), which is a crucial factor impacting IC reliability. EM refers to the degradation process of IC metal nets when used for both power supply and interconnecting signals. Typically, EM concerns have been addressed at the backend, circuit, and layout levels, where EM rules are enforced assuming extreme conditions to identify and resolve violations. This study presents new techniques that leverage architectural features to mitigate the effect of EM on the memory hierarchy of modern microprocessors. Architectural approaches can reduce the complexity of solving EM-related violations, and they can also complement and enhance common existing methods. In this study, we present a comprehensive simulation analysis that demonstrates how the proposed solution can significantly extend the lifetime of a microprocessor’s memory hierarchy with minimal overhead in terms of performance, power, and area while relaxing EM design efforts.

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Section: Prior Work On Electromigrationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Electromigration-Aware Memory Hierarchy Architecture

Gabbay

Mendelson

2023

JLPEA

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“…J tends to be much higher than J crit in interconnects (nearly 2 orders of magnitude [27]). Hence, J − J crit ≈ J. J for an interconnect can be related to the switching probability of the line p [28]:…”

Section: Lifetime Reliability Modelmentioning

confidence: 99%

Energy-Efficient Application Mapping and Scheduling for Lifetime Guaranteed MPSoCs

Liu

et al. 2019

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Energy optimization is one of the most critical objectives for the synthesis of multiprocessor system-on-chip (MPSoC). Besides, to ensure a long processor lifetime and to maintain a safe chip temperature are also important for multiprocessor manufactures under deep submicrometer process technologies. This paper presents a Mixed Integer Linear Programming (MILP) model to determine the mapping and scheduling of realtime applications onto embedded MPSoC platforms, such that the total energy consumption is minimized with the lifetime reliability constraint and the temperature threshold constraint satisfied. We develop a lightweight temperature model that can be integrated in the MILP model to predict the chip temperature accurately and efficiently. By exploiting the Dynamic Voltage and Frequency Scaling (DVFS) capability of modern processors, processor voltage/frequency assignment is also considered in our MILP model. Extensive performance evaluations on synthetic and real-world applications demonstrate the effectiveness of the proposed approach. Our MILP model achieves an average reduction of 19.09% and 28.53% total energy in comparison with two state-of-the-art techniques on the basis of guaranteeing the safe chip temperature and system lifetime reliability.

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Low-power encodings for global communication in CMOS VLSI

Stan

Burleson

1997

IEEE Trans. VLSI Syst.

160

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Technology trends and especially portable applications are adding a third dimension (power) to the previously two-dimensional (speed, area) VLSI design space [30]. A large portion of power dissipation in high performance CMOS VLSI is due to the inherent difficulties in global communication at high rates and we propose several approaches to address the problem. These techniques can be generalized at different levels in the design process. Global communication typically involves driving large capacitive loads which inherently require significant power. However, by carefully choosing the data representation, or encoding, of these signals, the average and peak power dissipation can be minimized. Redundancy can be added in space (number of bus lines), time (number of cycles) and voltage (number of distinct amplitude levels). The proposed codes can be used on a class of terminated off-chip board-level buses with level signaling, or on tristate on-chip buses with level or transition signaling. Index Terms-Global communication in VLSI, low-power encoding, low-power I/O, space encoding, time encoding, twodimensional (2-D) codes. I. INTRODUCTION T HE low-power community has been generally concerned with average power consumption and ways to minimize it. Average power is directly related to battery life in case of portable applications, as well as with costly package and heatsink requirements for high-end devices [24]. More recently the interest has also shifted to minimizing the instantaneous, or peak, power dissipation. There are cases when the instantaneous power can be much higher than the average power, and this leads to an undesired increase in simultaneous switching noise [14], metal electromigration problems [6], and local physical deformations due to nonuniform temperatures on the die. This paper focuses on low-power techniques for global communication in CMOS VLSI using data encoding methods. Such encodings can decrease the power consumed for transmitting information over heavily loaded communication paths (buses) by reducing the switching activity without affecting the I/O information entropy [17]. Some of the techniques presented here are particularly effective in reducing the peak power consumption. Global communication is typically achieved with buses [8], [7]. Such buses can be on-chip (between different functional Manuscript

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Electromigration reliability enhancement via bus activity distribution

Cited by 12 publications

References 8 publications

Electromigration-Aware Memory Hierarchy Architecture

Electromigration-Aware Memory Hierarchy Architecture

Energy-Efficient Application Mapping and Scheduling for Lifetime Guaranteed MPSoCs

Low-power encodings for global communication in CMOS VLSI

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