Electron valence-band tunnelling excess noise in twin-gate silicon-on-insulator MOSFETs

Simoen, Eddy; Claeys, Corneel; Lukyanchikova, N.; Garbar, N.; Smolanka, A.; Agopian, Paula Ghedini Der; Martino, João Antônio

doi:10.1016/j.sse.2005.10.038

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Introduction3

Figure 1 Fabrication Process Of Soi Technology1

V) For Both Nand P-mosfets1

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Cited by 11 publications

(12 citation statements)

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“…[9,8] the pair is then split apart, using a process that leaves a thin (relative to the thickness of the starting wafer), device-quality layer of single crystal silicon on top of the oxide layer (which has now become the BOX) on the handle wafer. This [10,11,12] is called the "layer transfer" technique, because it transfers a thin layer of device-quality silicon onto an oxide layer that was thermally grown on a handle wafer.…”

Section: Figure 1 Fabrication Process Of Soi Technologymentioning

confidence: 99%

A Theoretical Study of Low Power Soi Technology

Vandana¹

2013

(IOSR-JVSP

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Section: Figure 1 Fabrication Process Of Soi Technologymentioning

confidence: 99%

A Theoretical Study of Low Power Soi Technology

Vandana¹

2013

(IOSR-JVSP

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“…On the other hand, reducing the channel length causes an enhancement of the 1/f noise level, and this higher noise level probably masks the excess noise due to the GIFBE. The GIFBE in a twin-gate (TG) structure (Fig.4) is significantly reduced [5].…”

Section: V) For Both Nand P-mosfetsmentioning

confidence: 99%

Performance and new effects in advanced SOI devices and materials

Jomaah

2005

Microelectronic Engineering

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“…Recently, it has been reported that this structure also reduces the EVB related excess low frequency noise (7). It is important to note that the classical kink is caused by a high lateral electric field, while the LKE is due to a high vertical electrical field…”

Section: Introductionmentioning

confidence: 98%

Series Resistance Influence on the Linear Kink Effect in Twin-Gate Partially Depleted SOI nMOSFETS

Agopian

Martino

Simoen³

et al. 2007

ECS Trans.

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This work elaborates on the influence of the series resistance on the linear kink effect (LKE) in twin-gate partially depleted (PD) Silicon-on-Insulator (SOI) nMOSFETs. The study is based on two-dimensional numerical simulations and is validated by experimental results. A relationship between the total resistance and the apparent mobility degradation factor is reported, showing that the twin-gate structure and a conventional SOI transistor with an external resistance both present a similar LKE reduction. The asymmetric behavior of the body potential with the interchange of the master and slave transistor of the twin-gate structure will be also shown.

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Electron valence-band tunnelling excess noise in twin-gate silicon-on-insulator MOSFETs

Cited by 11 publications

References 16 publications

A Theoretical Study of Low Power Soi Technology

A Theoretical Study of Low Power Soi Technology

Performance and new effects in advanced SOI devices and materials

Series Resistance Influence on the Linear Kink Effect in Twin-Gate Partially Depleted SOI nMOSFETS

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