(Electronics & Photonics Division Award Presentation) Si-SiO₂ Interface to High-K-Ge/III-V Interface: Passivation and Reliability

Abstract

The Si-SiO2 interface is one of the most important semiconductor-dielectric interfaces that has been studied extensively over many decades. The understanding and control of structural and electronic properties of Si-SiO2 interfaces has provided many clues for technological advancement. The article discusses how the Si-SiO2 interface migrated through the technological landscape like plasma processing damage, hot carrier effects and negative bias temperature instability (NBTI) and subsequent passivation techniques using hydrogen to nitrogen. Introduction of high-k gate dielectrics brought significant attention to the interface between silicon and high-k dielectrics but Si-SiO2 interface continued to be important because of the presence of a SiO2-based interfacial layer. With deposition of high-k gate dielectrics high carrier mobility substrates (Ge/III-V) are currently being considered as the channel materials. To obtain a high quality interface between the high-k dielectrics and the high mobility substrates some issues like deposition process, precise selection of deposition parameters, predeposition surface treatments, appropriate passivation techniques and subsequent annealing temperatures are also outlined.

Emerging Applications for High K Materials in VLSI Technology

“…Ge also has some interesting benefits with ZrO 2 as the gate dielectric [87–89]. As with the III–V material systems discussed below the passivation of defects at the Ge/High K interface is a key challenge for any High K dielectric scheme used, which can be largely avoided by using a Si cap [90–94]. However, use of a Si cap for passivation has some detriments as well.…”

“…The possibility for III–V NFETs due to their high electron mobility has also been extensively investigated and reviewed [18,70,92,94,103–105]. A benchmark result reported by Intel in 2011 employed a quantum well structure within a Tri-Gate architecture and a TaSiO 4 gate dielectric [73].…”