SOI ESD design is distinct from bulk CMOS ESD design as a result of the buried oxide (BOX) film and the MOSFET floating body region [1,[2][3][4]. The BOX decouples the SOI n-and p-channel MOSFET body region from the silicon substrate [2][3][4]. The BOX region also separates and isolates the p-and n-channel SOI MOSFET. Many of the bulk ESD design practices are similar, but new issues need to be addressed in SOI ESD design. In SOI ESD analysis, active areas include SOI electro-thermal simulation and modeling [5-9], experimental work and design integration [11][12][13][14][15][16][17][23][24]27], and SOI patents [10,18,19,21,22,25,[26][27][28][29][30][31][32][33][34][35][36][37][38][39][40].Although many of the basic concepts of ESD design in SOI and bulk CMOS technology are similar, the actual physical layout of the structures and ESD network integration can be significantly different. This has led to the need for new semiconductor devices, new ESD design layout, and new circuit innovations.Some of the fundamental distinctions are as follows:No vertical parasitic devices exist.No lateral device exists without formation of a MOSFET gate structure; hence, SOI MOSFETs, diodes, and resistors utilize gate structures.Vertical shallow trench isolation (STI)-bound p þ anode/n-well cathode diode structure does not exist in SOI technology.n-well-to-substrate ESD diode elements do not exist in SOI technology.Parasitic CMOS-based pnpn structures do not exist in SOI technology.There are no vertical diode elements, hence no advantage to the area dependency in the design of structures.
ESD: Circuits and Devices Steven H. VoldmanThere are no guard ring structures needed in SOI technology.There are no local substrate contact guard rings for SOI devices.n-and p-well regions do not exist.Bulk ''floating gate tie-downs'' and well tie-downs do not exist.Unique electrical connections need to be established with the substrate region in SOI technology.As a result of the above issues, although the basic concepts in SOI ESD design are the same, there are significant differences in the physical layout and device choices [1]. Additionally, even with the direct mapping of circuits, the ESD response circuit can be significantly different, leading to new ESD issues and failure mechanisms.Where at first glance, the presence of the BOX appears to be a serious decrement to SOI ESD design [2-5], the issues above can lead to significant advantages over bulk CMOS silicon ESD design [1].The lack of vertical parasitic devices leads to a reduction of the complexity of device-todevice interactions. In bulk CMOS, a significant number of ESD failures and concerns are unanticipated interactions between adjacent elements and adjacent circuits; in SOI, this is not true. In bulk CMOS ESD design, the interaction between adjacent elements and circuits leads to complex ESD design rules and logical-to-physical checking computer-aided design (CAD) tools. In SOI, ESD design is significantly simplified because of the elimination of these unexpected interactions and cu...