elfPlace: Electrostatics-Based Placement for Large-Scale Heterogeneous FPGAs

Meng, Yibai; Li, Wuxi; Lin, Yibo; Pan, David Z.

doi:10.1109/tcad.2021.3053191

Cited by 15 publications

(17 citation statements)

References 35 publications

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“…RippleFPGA [23] GPlace [7] UTPlaceF [5] elfPlace [13] FTPlace [20] GPlace 3.0 [24] RippleFPGA Clock-Aware [11] UTPlaceF 2.0&2.X [9], [10] NTUfPlace [15] Lin et al [ total number of clock nets whose bounding boxes intersect with the clock region. The half-column constraint limits the number of clock nets within the half-column to a maximum of 12.…”

Section: Placermentioning

confidence: 99%

“…TABLE I summarizes the characteristics of the published state-of-the-art FPGA placers. In recent years, modern FPGA placers mainly resort to quadratic programming-based approaches [4]- [12] and nonlinear optimization-based approaches [13]- [15] for the best trade-off between quality and efficiency. Among them, the current state-of-the-art quality is achieved by nonlinear approaches elfPlace [13] and NTUfPlace [15], whose instance density models are derived from a multi-electrostatics system and a hand-crafted bellshaped field system.…”

Section: Problem Formulationmentioning

confidence: 99%

“…In recent years, modern FPGA placers mainly resort to quadratic programming-based approaches [4]- [12] and nonlinear optimization-based approaches [13]- [15] for the best trade-off between quality and efficiency. Among them, the current state-of-the-art quality is achieved by nonlinear approaches elfPlace [13] and NTUfPlace [15], whose instance density models are derived from a multi-electrostatics system and a hand-crafted bellshaped field system. However, most existing FPGA placers only consider a simplified FPGA architecture, i.e., LUT, FF, DSP, and BRAM, ignoring the commonplace SLICEL-SLCIEM heterogeneity in real FPGA architectures [5]- [11], [13]- [15].…”

Section: Problem Formulationmentioning

confidence: 99%

“…Among them, the current state-of-the-art quality is achieved by nonlinear approaches elfPlace [13] and NTUfPlace [15], whose instance density models are derived from a multi-electrostatics system and a hand-crafted bellshaped field system. However, most existing FPGA placers only consider a simplified FPGA architecture, i.e., LUT, FF, DSP, and BRAM, ignoring the commonplace SLICEL-SLCIEM heterogeneity in real FPGA architectures [5]- [11], [13]- [15]. Among these placers, only a few placers utilize the parallelism that the GPU provides [13], and few consider timing and clock feasibility in practice [8], [9], [11], [14], [15].…”

Section: Problem Formulationmentioning

confidence: 99%

“…The heterogeneity of the FPGA architecture comes from the variety of instance types, the imbalance of resource distribution, and the asymmetric slice compatibility from the SLICEL-SLICEM heterogeneity [19]. The diversity of instance sizes and the inconsecutive site compatibility challenge the modern FPGA placement algorithms, which are mainly based on continuous optimization [2], [13].…”

Section: Introductionmentioning

confidence: 99%

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Multi-electrostatic FPGA placement considering SLICEL-SLICEM heterogeneity and clock feasibility

Mai

Meng

et al. 2022

Proceedings of the 59th ACM/IEEE Design Automation Conference

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When modern FPGA architecture becomes increasingly complicated, modern FPGA placement is a mixed optimization problem with multiple objectives, including wirelength, routability, timing closure, and clock feasibility. Typical FPGA devices nowadays consist of heterogeneous SLICEs like SLICEL and SLICEM. The resources of a SLICE can be configured to {LUT, FF, distributed RAM, SHIFT, CARRY}. Besides such heterogeneity, advanced FPGA architectures also bring complicated constraints like timing, clock routing, carry chain alignment, etc. The above heterogeneity and constraints impose increasing challenges to FPGA placement algorithms.In this work, we propose a multi-electrostatic FPGA placer considering the aforementioned SLICEL-SLICEM heterogeneity under timing, clock routing and carry chain alignment constraints. We first propose an effective SLICEL-SLICEM heterogeneity model with a novel electrostatic-based density formulation. We also design a dynamically adjusted preconditioning and carry chain alignment technique to stabilize the optimization convergence. We then propose a timing-driven net weighting scheme to incorporate timing optimization. Finally, we put forward a nested Lagrangian relaxation-based placement framework to incorporate the optimization objectives of wirelength, routability, timing, and clock feasibility. Experimental results on both academic and industrial benchmarks demonstrate that our placer outperforms the state-of-the-art placers in quality and efficiency.

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